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Analog Verification >> Analog Functional Verification >> Proper modelling of a current source in verilogAMS.
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Message started by edstrom on Nov 28th, 2019, 3:29am

Title: Proper modelling of a current source in verilogAMS.
Post by edstrom on Nov 28th, 2019, 3:29am

Hi,

I am struggling with modelling a current source in verilogAMS.
An ideal current source with a load would be

      I(vdd, ibias)      <+  20e-6;
for a current pin ibias.

The problem with convergence comes with this implementation when the pin ibias is unloaded. The simulator will drive that current without any load, resulting in a very large voltage, resulting in a zero diagonal unsolvable matrix.

What would be necessary, is to model the output impedance properly.
I have tried to short the output through a large resistor.

      V(ibias,vss) <+I(ibias,vss)*100e6;

But the above statement still drives the current to the output ibias, generating convergence issues.

What would be the proper way to model this?

Title: Re: Proper modelling of a current source in verilogAMS.
Post by Ken Kundert on Nov 29th, 2019, 10:58am

You can add a resistive clamp:

Code:
I(vdd,ibias) <+ 20u;
if (V(vdd,ibias) < 0)
   I(vdd,ibias) <= V(vdd,ibias)/1k;


Not sure that code is right. I am in an airport and cannot try it. Bascially, it is designed to add a 1k resistor connected to Vdd when ibias goes above Vdd.

-Ken

Title: Re: Proper modelling of a current source in verilogAMS.
Post by edstrom on Dec 2nd, 2019, 11:39pm

Thanks Ken,

I tried your code snippet with some minor syntax changes. And i still experience convergence issues in the node ibias.

I to me, it makes sense. Because i will still drive a current from supply to a floating node

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