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Design >> Analog Design >> Scaling of Sampling clock in CT-SDM ADC
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Message started by neoflash on Jan 2nd, 2020, 4:23pm

Title: Scaling of Sampling clock in CT-SDM ADC
Post by neoflash on Jan 2nd, 2020, 4:23pm

If I want to optimize for area, does it make sense to push the sampling clock the higher end?

Assuming SQNR is sufficient, and output sample rate is fixed. If I double Fs, I can shrink integrator Cap by 2x.

Other performances:

- Noise is not changing as R/gm doesn't really change
- OSR is 2x but little impact on perf as Q noise is small
- excess delay can be compensated

any other item that I missed? Thanks.

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