The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> High-Speed I/O Design >> Why SPI chip select signal is active low?
https://designers-guide.org/forum/YaBB.pl?num=1578330286

Message started by neoflash on Jan 6th, 2020, 9:04am

Title: Why SPI chip select signal is active low?
Post by neoflash on Jan 6th, 2020, 9:04am

Is this an arbitrary choice or has some electrical reason behind it?

Thanks,
Neo

Title: Re: Why SPI chip select signal is active low?
Post by Frank Wiedmann on Jan 8th, 2020, 7:39am

A quick search turned up this on https://electronics.stackexchange.com/questions/7664/why-are-things-like-reset-mclr-active-low-on-most-ics:

Wikipedia says (http://en.wikipedia.org/wiki/Logic_level):

Many control signals in electronics are active-low signals (usually reset lines, chip-select lines and so on). This stems from the fact that most logic families can sink more current than they can source, so fanout and noise immunity increase. It also allows for wired-OR logic if the logic gates are open-collector/open-drain with a pull-up resistor. Examples of this are the IC bus and the Controller Area Network (CAN), and the PCI Local Bus. RS232 signaling, as used on some serial ports, uses active-low signals.

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.