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Design >> Mixed-Signal Design >> clocking of a decimation filter and reading the output of a decimation filter
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Message started by polyam on Jan 23^rd, 2020, 5:24pm

Title: clocking of a decimation filter and reading the output of a decimation filter
Post by polyam on Jan 23^rd, 2020, 5:24pm

Hi everyone,

I have questions related to a delta sigma modulator followed by an on-chip decimation filter.

1- I have a master clock (mclk) and I am generating two non-overlapping clocks and their delayed versions (let's call them phi1,phid, phi2 and phi2d). Can I use mclk as the clock signal for my decimation filter? Can any one comment on how the modulator and decimation filter could be in the same clock domain? Do essentially they need to be in the same clock domain?

2- My modulator is a single bit modulator (outp and outn are the output of the modulator coming out of a regenerative latch followed by a SR-latch). How would be the connection between the outputs of the modulator and the input of the decimation filter? Should I connect either of them (outp or outn) to the decimation filter or I have to connect the differential version of the output to the decimation filter?

3- I am reading 16bit decimation filter output from an on-chip SPI. To de-risk, I want to read the 16-bit data from just one pad (I just have one pad available and I am muxing test points through it). that being said, can I use parallel to serial converter to read 16-bit output of the decimation filter through just one pad?

Thanks