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Measurements >> Phase Noise and Jitter Measurements >> determining jitter contribution from individual PLL block
https://designers-guide.org/forum/YaBB.pl?num=1580549545

Message started by thewirehead on Feb 1^st, 2020, 1:32am

Title: determining jitter contribution from individual PLL block
Post by thewirehead on Feb 1^st, 2020, 1:32am

Hey there,
I'm in the middle of 2.4GHz Integer PLL, Reference clock is 150MHz and Feed back divider is 16. Currently I'm getting rms period jitter of 1.2ps (please let me know if rms of period jitter plot (from virtuoso calculator) is good enough).

My question is how do i determine the jitter contribution from individual PLL block, such as per divider, post divider, feedback divider, LPF, charge pump and VCO (VCO I usually run PSS PNOISE and see Jee/Jcc)? this is my biggest concern, please help.

Please help me answering both the questions. Thanks a lot in advance

cheers :) :)