The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Behavioral Models >> how to deal with segmentation fault in veriloga simulation
https://designers-guide.org/forum/YaBB.pl?num=1583376880

Message started by Bisharp on Mar 4^th, 2020, 6:54pm

Title: how to deal with segmentation fault in veriloga simulation
Post by Bisharp on Mar 4^th, 2020, 6:54pm

Does anyone ever meet the (SPECTRE-18) segmentation fault ?
I try to write a detector as follow to help me print the output data. and when i run the simulation in spretre, a fatal error:
"Encountered a critical error during simulation. Please run `mmsipack" to pack the test case... FATAL(SPECTRE-18):Segmentation fault."
I found some explanation that the segmentation fault is due to the wrong usage of memory. but i am still confused in my case...

Title: Re: how to deal with segmentation fault in veriloga simulation
Post by Andrew Beckett on Mar 5^th, 2020, 6:54am

Well, the message asks you to use mmsimpack to package up the test case and contact customer support. So that's the best thing. A segmentation fault shouldn't happen - it indicates the program is accessing memory it shoudn't.

Does it print progressively longer strings and then fails when the string gets very large? I'd try it out, but I don't want to spend time re-typing in your code (screenshots are not very useful for this... better to paste the code into the post and use the "Insert Code" icon around it (the # symbol in the icons when creating your post).

Anyway, contacting http://support.cadence.com would make most sense.

Andrew

Title: Re: how to deal with segmentation fault in veriloga simulation
Post by Bisharp on Mar 5^th, 2020, 7:20am

Andrew Beckett wrote on Mar 5^th, 2020, 6:54am:

Thank you Andrew, your advice is realy nice to me (as a newbie). and I will remember that.
in my testbench, i set the trans. simulation time to 800p, and set the parameter "peiod" to 10p; The input "data" is a square wave with a period of 10p;

Code:

module datadet(data);
input data;
electrical data;
parameter real vh =1 from [0:inf);
parameter real vl = 0 from [0:inf);
parameter real vth = (vh+vl)/2;
parameter real start_time = 0 from [0:inf);
parameter real period = 10p from (0:inf);
integer cmp;
string data_flow,a;
analog begin
@(initial_step)
data_flow="";
@(timer(start_time, period)) begin
cmp = (V(data)>vth);
$sscanf(a,"%d",cmp);
data_flow = {data_flow,a};
$strobe("the data in %M is %s", data_flow);
end
end
endmodule

Title: Re: how to deal with segmentation fault in veriloga simulation
Post by Bisharp on Mar 5^th, 2020, 7:41am

As above mentioned, in my understanding, the timer command only repeat nearly 80 times, the string “data_flow” is only a combination of 80 bits number，how could it accessing forbidden memory. I am confused...

Title: Re: how to deal with segmentation fault in veriloga simulation
Post by Andrew Beckett on Mar 8^th, 2020, 3:16am

I'd hypothesised that the problem was caused by repeatedly extending the string data_flow and this was triggering a bug in Spectre (a segmentation fault is a clear indication of a simulator bug - but of course it's triggered by something specific in the code).

From doing some debugging, I found that the issue is not with the string concatenation but the $sscanf. In fact you really don't want $sscanf here, because that would be parsing the string a, trying to find an integer within that, and putting the result in the integer variable cmp. Instead, you want to go the other way, so you should be using $swrite rather than $sscanf:

$swrite(a,"%d",cmp);

If you do that, the code runs with no problems. The crash is actually a problem if sscanf tries to parse an uninitialised string (if a is set to "" or "1" beforehand it runs without the crash, but then the code doesn't do what you want).

I filed a Cadence Change Request, 2233969, to get the crash fixed (because it makes it hard to diagnose the true problem, which is the incorrect function being used). Hopefully everything works for you with $swrite instead of $sscanf.

Regards,

Andrew.

Title: Re: how to deal with segmentation fault in veriloga simulation
Post by Bisharp on Mar 8^th, 2020, 4:03am

Andrew Beckett wrote on Mar 8^th, 2020, 3:16am:

Thank you very much for your detailed and patient answers. It really helps me better understand this error!

-Ying