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Design >> RF Design >> How to ensure the pll loop stability with VCO gain variation?
https://designers-guide.org/forum/YaBB.pl?num=1599309946

Message started by tulip on Sep 5^th, 2020, 5:45am

Title: How to ensure the pll loop stability with VCO gain variation?
Post by tulip on Sep 5^th, 2020, 5:45am

I designed a PLL, the VCO's control voltage Vtune is in the range of 0.7V~2.5V, the VCO(ring VCO) can oscillate from 10M to 1.2G, the target frequency of VCO is 500M, when the PLL locks, the Vtune is about 1.2V.
The problem is: the VCO gain at Vtune =0.7 or 2.5 (two ends of the tuning range) is very low, especially at Vtune =0.5, the VCO gain is 100M/V, while at Vtune=1.2, the VCO gain is 680M/V, consider about process corner and temperature variations, the VCO gain variation is much bigger.

I designed the loop filter, which can ensure stability when VCO gain is among 300M/V to 1.4G/V, but at low end of the VCO tuning range(Vtune=0.7) , the VCO gain is 100M/V, the pLL is not stable.

At the PLL taget frequency, the VCO tune voltage is between 1~ 1.2V, far away from the low end of the VCO tuning range.

My question is : Will my PLL work properly? when vtune is 0.5V(at this vtune voltage, the PLL loop can be unstble), can it converge to the target voltage of 1.2V?

Thank you.