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Design >> Mixed-Signal Design >> How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
https://designers-guide.org/forum/YaBB.pl?num=1601663609

Message started by iVenky on Oct 2^nd, 2020, 11:33am

Title: How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
Post by iVenky on Oct 2^nd, 2020, 11:33am

Hi,

I am wondering if it makes sense to define a DNL/INL for a 1-bit delta sigma ADC (1-bit comparator) for a DC input? Since the data is processed after a digital filter and we could have a ±1 LSB error (meaning if the input is like 1LSB + Δv, we could have 1LSB or 2LSB at the output of delta-sigma without a 1-1 mapping due to limit cycles unlike other ADC architectures where is a 1-1 mapping), is there a way to define DNL/INL for a DC input? Does it make sense?

Title: Re: How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
Post by Rakesh on Oct 7^th, 2020, 8:34pm

Single bit DSM inherently is linear as it has two points. So it doesnt give DNL of INL. However the amplifier nonlinearity etc can introduce nonlinearity.

Also for single bit DSM gain is not defined

Title: Re: How do you simulate or define DNL/INL for a 1-bit Delta Sigma ADC for a dc input
Post by iVenky on Oct 12^th, 2020, 3:50pm

Thanks Rakesh! Yes, so it means it makes no sense to define DNL/INL for a single-bit delta-sigma, right?