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Design >> Analog Design >> Questions on Sub-1 Volt OTA
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Message started by blue111 on Jun 18^th, 2021, 3:05am

Title: Questions on Sub-1 Volt OTA
Post by blue111 on Jun 18^th, 2021, 3:05am

Could anyone explain on "Obviously, the compensation capacitance CC does not connect Drain to Gate directly around output transistor M10. It takes a path through cascode device M6, in order to avoid a positive zero. " ?

Title: Re: Questions on Sub-1 Volt OTA
Post by Ken Kundert on Jun 18^th, 2021, 12:53pm

The desired effect of the compensation capacitor is to feed back some of the output signal back into an earlier stage. However signals can flow both ways. As the gain of the second stage drops at high frequencies, the signal at the left side of the capacitor can be larger than that on the right side. As a result, signal flow reverses and now the output is driven more by the compensation capacitor than the output stage. This has two effects. First, the gain levels off, which creates a zero as can be seen by examining the magnitude in a Bode plot. Second, by bypassing the output stage, which is inverting, the sign of the signal reverses. This creates an additional 90 degrees of phase shift. In effect, has the look of a zero if you examine the magnitude of the gain versus frequency, but it has the look of a pole if you examine the phase. In reality this is a right-hand plane zero (or RHPZ or positive zero).

To increase the frequency of the RHPZ so that it does not interfere with the stability of the loop, the designer has connected the compensation capacitor to a low-impedance node. The signal level will be relatively small there, reducing the effect of the feed-forward path through the capacitor. This will substantially raise the frequency of the RHPZ to the point where it is well beyond the unity gain frequency. With this modification, the RHPZ no longer degrades the stability of a loop built with the OTA.

For more, see https://www.allaboutcircuits.com/technical-articles/the-right-half-plane-zero-and-its-effect-on-stability

-Ken

Title: Re: Questions on Sub-1 Volt OTA
Post by blue111 on Jun 19^th, 2021, 2:40am

Someone told me that the circuit is using Ahuja compensation
However, I am not sure how it works

Title: Re: Questions on Sub-1 Volt OTA
Post by blue111 on Jun 20^th, 2021, 1:29am

For those interested in Ahuja compensation, Baker's uses "indirect compensation" in his book : CMOS: Circuit Design, Layout, and Simulation , see page 813, 814 and 815

@kundert

As for equation 12 inside https://www.allaboutcircuits.com/technical-articles/pole-splitting-and-miller-frequency-compensation/ , I do not understand what the sentence downshift ω10 → ω1 must be accompanied by an upshift ω20→ω2. is actually trying to convey. Why there is a guaranteed frequency downshift for the dominant pole, ω1 after adding miller capacitance ?

Title: Re: Questions on Sub-1 Volt OTA
Post by blue111 on Jun 20^th, 2021, 6:24pm

I got it now. It is due to dominant pole created out of the miller capacitance which generalizes to pole splitting effect as described by equation 12.

By the way, I created an actual mosfet circuitry implementation.

However, the transient analysis result look wrong.

Title: Re: Questions on Sub-1 Volt OTA
Post by A Kumar R on Nov 9^th, 2021, 2:53am

Ken,

Why did you say "As the gain of the second stage drops at high frequencies, the signal at the left side of the capacitor can be larger than that on the right side"....i think that by the time second-stage gain dropped, the first stage gain would have dropped a lot because the gain roll-off started earlier in frequency because it must be the dominant pole?. This means that signal on the left-side of the cap can never be larger than on the right-side.

Please clarify.

Thanks,
Anil