The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in https://designers-guide.org/forum/YaBB.pl?num=1636713101 Message started by bernd2700 on Nov 12th, 2021, 2:31am

 Title: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Nov 12th, 2021, 2:31am I indeed found a much simpler and clearer formulation of my core question, here it is (but therefore without all the Matlab equation proofes, these can be found in my detailled post some days ago). Root-spectral density @ low frequencies obtained with Cadence PNoise analysis for the following:Track-and-Hold circuit stand-alone:T&H stand-alone:               (Node “Vcs”):          ~ 45.4 nV/sqrt(Hz)Sampled with Ideal S&H:    (Node “Vcs_ext”):    ~ 90.3 nV/sqrt(Hz)     ((See attached picture 1))Complete integrator circuit:Node “Vo” :         903 uVrms/sqrt(Hz)Node “Vo_ext” :   903 uVrms/sqrt(Hz)     (here exactly the same as the result for node “Vo”)     ((See attached picture 2))If we divide this result by the open loop gain of 10000, we get again the 90.3 nVrms/sqrt(Hz). So with just now adding the (lossy, open-loop) integrator to the stand-alone T&H, the whole circuit now suddenly resembles a Sample & Hold (S&H), not anymore a T&H. Why?? The first part is still a T&H circuit! What is a correct theoretical model for this complete stuff?Thank you very much for any answer, any hint, anything in advance!Bernd2700

 Title: Re: Summarized phrasing of my core question "kT/C noise combined with an integrator" Post by bernd2700 on Nov 12th, 2021, 2:32am Complete integrator

Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in
Post by Ken Kundert on Nov 12th, 2021, 12:29pm

Quote:
 the whole circuit now suddenly resembles a Sample & Hold (S&H), not anymore a T&H. Why??

The difference between your T&H and your S&H is that the duty cycle of the output of the T&H is roughly 50% whereas the duty cycle of the S&H is roughly 100%.  That explains why the noise the output of the T&H is roughly half that of the S&H.

Your integrator is acting as a S&H.  The duty cycle at the output the integrator is roughly 100%.

You do not need pnoise to see this phenomenon. You can also see it with a PAC analysis.

-Ken

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by Ken Kundert on Nov 16th, 2021, 10:32pm Too many questions all at once.  I need to focus on one at a time.  So lets focus on #1.The integrator samples its input when the switch closes. At that time the output voltage changes so that all the charge on Cs flows onto Cf. Once equilibrium has been reached, the output remains unchanged even when the opens again.  This is the behavior of a sample & hold.  The input is sampled when the switch closes and the output is held until the next sample.This contrasts with the input stage. There, when the switch closes the stage goes into track mode and the output of the state tracks the input.  When the switch opens the stage goes into hold mode.-Ken

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Nov 22nd, 2021, 3:55am Dear Ken ( & others),Thank you for your reply! Ok, let’s proceed to question 2:I have drawn a detailed timing diagram of the circuit for that.((see attached timing diagram))What we see happening in the real circuit: First comes the input tracking phase. Then, as soon as switch 1 ( = switch connected to phase 1) opens = going to low state at time point #1, also the sampling occurs. The voltage on the cap “Cs” ( = Vcs) remains now constant ( = the on-state resistor noise is gone) until time point #2. Here, phase 2 gets high and switch 2 closes, resulting in an instantaneous charge sharing between the 2 capacitors. Then the integration phase follows.What could happen / happens conceptually? :So, the timing diagram produces the following sequence: First comes the tracking phase, then the sampling, then, finally, if we leave out the charge sharing phase, the integrating phase (and so the voltage amplification between the 2 caps).Because you, Ken, confirm, that the whole circuit “is acting as a S&H”, I am thinking that option a) could be fine for a valid model to obtain the output-referred noise?! So, I followed the steps according to option a) by equations (in Matlab):Step (1.) Building “kT/C noise together with a S&H”: ([Basically from Ken Kundert’s paper])m_SH = 0;   % Duty-cycle, for the S&H it is 0.Vn_SH_RSD_vec = sqrt( ((1-m_SH)*sinc(f_vec.*(1-m_SH)*Ts)).^2*2*k*T/(Cs*fs) );           % [Vrms/sqrt(Hz)]Step (2.) Building the “transfer-function (tf) of a lossy integrator”:f = 1 - 1 / ( Aol / ( Cs / Cf ) );      % Models lossy (= limited DC-gain) integrator.Int_z = - Cs / Cf * z.^-0.5 ./ ( 1 - z.^-1 * f);  % This is the exact model (with "z^-0.5") for this type of circuitStep (3.) = (1.) * (2.) = Multiplying the “(kT/C noise with S&H)” with the “(tf. of the integrator)”:kTCs_only_SH_times_tf_Integrator_DT = Vn_SH_RSD_vec' .* abs(Int_z');Step (4.) Plot:semilogx( f_vec , 20*log10( kTCs_only_SH_times_tf_Integrator_DT ) , 'r' , 'LineWidth' , 3 );==> Is my thinking = the resulting block diagram option a) correct for this circuit? Please “confirm” or “disagree”!==> Why then the Cadence PNoise result show nulls (= sudden drop downs) at fs = 1 kHz, 10*fs, 100*fs? (See thick black line, recalling the picture from my previous, detailed, post.) However, in the theoretical (Matlab) tick red line these are missing. Why? So: Am I doing here conceptually something wrong with taking “option a)” as a model for this circuit or are these nulls just an artefact of the Cadence PNoise analysis?

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Nov 22nd, 2021, 4:00am Recalling the picture again from my previous (detailed) post: ((Picture: "Fig8 kTC noise only with subsequent integrator.jpg"))

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by Ken Kundert on Nov 24th, 2021, 11:35pm I am not going to check your equations and your models. That would take too much time.The block diagram looks right.The nulls in the transfer function at 1 kHz, 10*fs, 100*fs is a plotting artifact.  There are actually sin(x)/x nulls at multiples of the clock frequency, but you are not using enough points in the plot to see all the nulls.

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Dec 10th, 2021, 8:03am Cadence_Cs_Cf_1F_PAC_results_Nodes_Vo_Vo_ext.png

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Dec 10th, 2021, 8:03am Cadence_Cs_Cf_1F_PAC_results_Nodes_Vcs_Vcs_ext_Vcs2_Vcs2_ext.png

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by Ken Kundert on Dec 10th, 2021, 11:25pm I'm afraid I have no experience with sampled PAC and cannot offer much. Nulls that go to infinity (poles) suggest that there is some normalization occurring, and the normalization is going to zero at those frequencies.  You should look more closely to see if they are really going to infinity, or to the dc gain of the amplifier.  Its not clear from the graph.As for the nulls being a display artifact, I have experienced them many times and they have always turned out to be so.  And when using a logarithmic sweep it is common to only see the nulls every factor of 10.  I recommend that you request many more points and then zoom in.  You can also try switching to a linear sweep and make sure there are points at all the harmonics of the clock.-Ken

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Dec 21st, 2021, 5:38am Dear Ken (and others),Thank you for your valuable hint to closer check if the “nulls” really go to “+ infinity” or just reach the “Aol” (open loop opamp DC gain) level, and, indeed, they just go up to Aol level which is 80 dB in this demo example.With this hint, I came further in my thinking and so managed to answer my first of the 2 questions by myself, and I want to herewith give back some knowledge for the others, if someone will have similar questions in the future:1. Why for some nodes, the “Nulls go UP ( = to + inf.) instead of DOWN (= to – inf.)?First, as just confirmed, they only go up to "Aol", not to "+inf". At the end, it’s very simple: Because theory says so. Also as said, I am interested in the Discrete-Time (DT) frequency response. And this forces symmetry around the (sampling) frequency “fs/2”. And so, if the DC gain is 80 dB, it must be as well 80 dB at fs. Therefore, the magnitude must go UP again from fs/2 onwards, not further down. All this can be seen very nicely from theory from the lossy “f” - term in the follwing (Matlab) equation, as e.g.:Int_z = - Cs / Cf * z.^-0.5 ./ ( 1 - z.^-1 * f );f = 1 - 1 / ( Aol / ( Cs / Cf ) );z = exp( j * w_vec * Ts );Thus, this is not an “artefact” or “strange behavior”, it must be like that.2. Why the “Nulls at every 10*fs are much stronger than every 1, 2, 3 * fs”?This stuff is indeed a plotting artefact. As Ken describes, if you are doing a linear frequency sweep (instead of log) and give the simulator really enough calculation points especially around the multiples of fs (to be concrete for the other readers here in my trial case 1000 points from 1.9 ... 2.1 kHz), one will see indeed that all the “nulls” at integer multiples of fs (so 1, 2, 3, ... * fs) go up to Aol, not only the ones at 1, 10, 100 ... * fs. (So 1000 points per decade (on log scale) was still to few.) Also this behavior is “forcasted” by theory: The pattern not only is symmetrical around fs/2, but also repeats with integer multiples of fs. Thus, also at 1, 2, 3, ... * fs the magnitude must reach the DC open loop opamp gain, here 80 dB. If this is not reached, you don't have enough sim. points or better said, the calculation point of the simulator is not exactly at 1, 2, 3, ... * fs.Nice greetings,bernd2700

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Jan 11th, 2022, 7:28am Dear Ken (& others),However, one question remains to this whole topic.In short:The real Cadence switched-cap. (SC.) integrator circuit (from the previous posts ; in below graph in green color) modelled by ...a) ... a pure Discrete-Time (DT) integrator Matlab model (in “z”) is fine and I understand all effects (red).b) ... a Continuous-Time (CT) integrator Matlab model (in “s”) which is then sampled by a ZOH (S&H) to get the DT response:   ==>   Why the hell it seems I have to DIVIDE by the ZOH (S&H) transfer-function and NOT to MULTIPLY by it to get matching results (blue) to the Cadence SC circuit (green)??  (Bode diagram magnitude at least)In more detail:That others can follow, I now describe this question a bit in-depth:A Zero-Order-Hold (ZOH) (Sample & Hold S&H) block stand-alone:First, we watch the Bode plot for this block stand-alone: The “nulls” go DOWN to –INFINITY (Here, because of “only” 1meg. points/dec., the first ones just go down to ca. -125 dB.). We see, at fs/2 its Bode plot has a gain of ca. -4 dB and a phase shift of -90° compared to the DC value of 0 dB / 0°.(Source: "https://electronics.stackexchange.com/questions/206482/exactly-what-is-the-role-of-the-zero-order-hold-in-a-hybrid-analog-digital-sampl": "Many textbooks leave out the T factor in the denominator of the transfer function and that is a mistake.": (1-exp(-s*Ts))/(s*Ts);)My real Cadence SC. integrator circuit (= my reference ; green):In the attached figure, the real Cadence sw.-cap. circuit (in green color) shows that the “nulls” at 1, 2, 3 ... * fs go UP, but only to +80 dB = to the DC-gain of the integrator, as it can be read in the previous posts. To obtain this Bode plot, as said, I do the “PAC sampled” analysis. This SC. circuit is my reference, and this I want to model with the following models:Pure DT integrator model (in “z”) (red):In a DT (discrete-time) model in “z” - domain, the “nulls” also go UP and also to this +80 dB level because theory says so (symmetry around fs/2 as presented in my previous post). In this pure DT model, the integrator has unlimited speed, therefore there is no kink visible at ~ 100 kHz.CT integrator model (in “s”) DIVIDED by the ZOH (S&H) block (blue):Here, I would like to model my real Cadence SC. circuit with a Continuous-Time (CT) integrator (in “s” - domain) Matlab model. To account equivalently for the “_SAMPLED” option of the Cadence PAC analysis in the real circuit also in this model, for me, this means (maybe I am wrong here??) I logically would have to subsequently MULTIPLY the integrator output by the S&H transfer function. This is my interpretation, because the strange thing is (= above question), obviously, I have to DIVIDE the integrator output by the ZOH transfer function, and not to multiply by it in order that the “nulls” go also up, and not down, as in the S&H stand-alone case. Then the Bode diagram of this result (blue color) matches approx. the real Cadence SC. circuit (green), apart from the nulls going up higher than just to the +80 dB DC gain limit. Of course, then, there is no symmetry around fs/2 anymore, since the open-loop DC gain is just +80 dB and in this model, the nulls go up, but to +infinity, not to just +80 dB (ok, I also do not have a DT signal which is valid only at 1/fs time points but still a CT signal whose value is held constant until the next point in time). However,==> What is wrong with this procedure for a CT model / how to do correctly?Thanks for any hint in advance,bernd2700

 Title: Re: Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in Post by bernd2700 on Jan 11th, 2022, 7:36am Fig31 - ZOH or SandH Stand-alone Bode-plot ScrSh02.png