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Design Languages >> Verilog-AMS >> Error in Unary negation operator in VerilogA designing charge pump
https://designers-guide.org/forum/YaBB.pl?num=1643873885

Message started by kankanas on Feb 2^nd, 2022, 11:38pm

Title: Error in Unary negation operator in VerilogA designing charge pump
Post by kankanas on Feb 2^nd, 2022, 11:38pm

Hello all,

I need help understanding the reason for the error, that I am getting for using the unary negation operator in VerilogA code. I went through the verilogA reference material, but I am getting no clue.

I will be helpful in getting a reply.

Title: Re: Error in Unary negation operator in VerilogA designing charge pump
Post by Ken Kundert on Feb 3^rd, 2022, 8:18pm

The model appears to be a Verilog-AMS model, not a Verilog-A model. Are you really simulating it with Verilog-A?

If you are really using Verilog-A, you might want start with Listing 10 in https://designers-guide.org/analysis/PLLnoise+jitter.pdf and strip out the jitter modeling.

Note the use of cross functions. Those are important to resolving the exact time when the thresholds are crossed. Without those you will be subject to high-levels of jitter that stems from finite time steps of the simulator.

Also, notice that the transition function is not in a conditional. Transition function should not be in conditionals or loops. Instead, assign the current to a variable, and then use that variable to drive a transition function outside the if statement.

-Ken

Title: Re: Error in Unary negation operator in VerilogA designing charge pump
Post by Geoffrey_Coram on Feb 10^th, 2022, 1:40pm

The (incorrect) indentation of the original model looks like the transition() function is in a conditional (along with the contribution), but it is not. The code should be indented differently for better readability:

Code:

if(!up && down)
out = -cur;
else if(!down && up)
out = cur;
else
out = 0;
I(pout, nout) <+ transition(out, 0.0, 20p, 20p);

But, as Ken notes, this doesn't look like true Verilog-A. You have "up" and "down" appearing in the if conditions, without the access function, and actually you haven't set a discipline for them (you set pout and nout to be electrical). I would expect a true Verilog-A model to have "electrical up, down;" and then access them with V(up) and V(down), perhaps comparing them with a threshold.

Based on the highlighting in the screen-shot, it seems the problem is with up and down, not with the unary minus sign.