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Design >> RF Design >> What's the timing window to update dual-modulus divider divider ratio control?
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Message started by neoflash on Sep 20^th, 2022, 7:40pm

Title: What's the timing window to update dual-modulus divider divider ratio control?
Post by neoflash on Sep 20^th, 2022, 7:40pm

In frac-N PLL, if I use dual-modulous divider as shown in the figure, what is the safe time window to update the divider ratio control word P<N:0>?

Intuitively the safe window is to update the p<n:0> when all mod0-modn signals are logic low. Not sure if this is correct and can assure the divider operates glitch-free.

Thanks,
Neo

Title: Re: What's the timing window to update dual-modulus divider divider ratio control?
Post by smlogan on Oct 29^th, 2022, 6:06pm

Dear neoflash,

> if I use dual-modulous divider as shown in the figure, what is the safe time
> window to update the divider ratio control word P<N:0?
>
> Intuitively the safe window is to update the p<n:0> when all mod0-modn signals
> are logic low. Not sure if this is correct and can assure the divider operates
> glitch-free.

An approach I have used is to synchronize the divider option. p(N:0>, to the output clock. There will still exist a maximum input frequency, but this approach worked well for me.

Shawn