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Design >> Analog Design >> any analysis paper on stack mos array?
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Message started by neoflash on Oct 5^th, 2022, 9:08pm

Title: any analysis paper on stack mos array?
Post by neoflash on Oct 5^th, 2022, 9:08pm

Like how to calculate the stack mos gm, gds, vdsat and etc?

Thanks!

Title: Re: any analysis paper on stack mos array?
Post by dpalma on Jan 24^th, 2023, 2:43am

Also interested in this topic. A drop here a reference I found helpful

D. Lee and J. Han, «Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology», 18th International SoC Design Conference (ISOCC), 2021. doi: 10.1109/ISOCC53507.2021.9613881.

Title: Re: any analysis paper on stack mos array?
Post by davidshw on Feb 5^th, 2023, 7:49pm

This paper may be helpful.

C. Galup-Montoro, M. C. Schneider, and I. J. Loss, ‘Series-parallel association of FET’s for high gain and high frequency applications’, IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1094–1101, 1994.