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Design Languages >> Verilog-AMS >> a behavioral model to measure a SMPS like buck converter's loop
https://designers-guide.org/forum/YaBB.pl?num=1667281859

Message started by RobertD on Oct 31^st, 2022, 10:50pm

Title: a behavioral model to measure a SMPS like buck converter's loop
Post by RobertD on Oct 31^st, 2022, 10:50pm

Hi,

I am wondering if there is a behavioral model to plot a SMPS like buck converter's loop in transient simulation like below website.
https://www.analog.com/en/technical-articles/ltspice-basic-steps-in-generating-a-bode-plot-of-smps.html

Thanks!

Title: Re: a behavioral model to measure a SMPS like buck converter's loop
Post by Geoffrey_Coram on Mar 6^th, 2023, 7:58am

The link you shared shows that the simulator in question supports ".fra" as a new analysis type. This is outside the scope of a hardware description language like Verilog-AMS, which does not require a simulator to support specific analysis types.
Probably one could develop a model that would be helpful in generating the plot, but you'd need some extra code, either in the simulator or in a post-processing tool.