Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Assura RCX fails with Generic PDK 45nm	kmmankad	1	878	Mar 7^th, 2013, 8:13am By: bernd
LPE and PRE in Dracula	Yutao Liu	0	1989	Feb 3^rd, 2013, 1:37am By: Yutao Liu
Extracting board parasitics in Cadence virtuoso environment	rajdeep	2	4764	Jan 28^th, 2013, 6:08am By: rajdeep
How to position the segment of one metal line in RC extraction	ywguo	0	1715	Dec 14^th, 2012, 6:20pm By: ywguo
Assura LVS: issue with hierarchy	rho	1	4248	Sep 18^th, 2012, 3:14am By: boe
questions about extract layout with calibre	easyads	1	5056	Aug 11^th, 2012, 5:37pm By: Maks
how can i use �asitic �to simulate and design the PGS inductor on chip	coolliu	0	1936	Jul 17^th, 2012, 7:09pm By: coolliu
Assura LVS cdl file is not right	cgikun	0	2362	Jul 6^th, 2012, 9:50pm By: cgikun
Calibre PEX issues	varun patial	0	2242	May 17^th, 2012, 11:36am By: varun patial
Conversion of extraxted view generated in calibre to extracted view in cadence..	varun patial	0	1818	May 9^th, 2012, 10:07pm By: varun patial
Sonnet and Momentum	fab32	0	3062	May 9^th, 2012, 12:21pm By: fab32
Calibre PEX annotation back schematic	ywguo	5	1516	May 2^nd, 2012, 6:50pm By: Daniel Lai
Error during ASSURA parasitic extraction.	VINAY RAO	1	4525	Mar 6^th, 2012, 7:20am By: boe
Assura LVS debugging	jak	10	2634	Feb 29^th, 2012, 7:33am By: VINAY RAO
Difference between N/P �select and n/p - active layers in CMOS layout techniques	VINAY RAO	1	2565	Feb 24^th, 2012, 7:29am By: Geoffrey_Coram
Layout extraction	raja.cedt	2	869	Jan 18^th, 2012, 6:19am By: Frank Wiedmann
Ref Node in Assura RCX	ywguo	0	2397	Dec 30^th, 2011, 11:06pm By: ywguo
HFSS antenna design procedure.	Habib Ullah	0	2415	Nov 24^th, 2011, 1:29am By: Habib Ullah
layout to schematic problem	lanfird	1	2818	Sep 30^th, 2011, 7:30am By: ywguo
about starrc XREF problem	lhlbluesky_lhl	1	737	Sep 27^th, 2011, 6:10am By: lhlbluesky_lhl

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