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Subject	Started by	Replies	Views	Last post
Moved: ADC verification in cadence - Started by: jesseyu This Topic has been moved to Circuit Simulators by Ken Kundert
capacitor matching	aaron_do	7	6290	Mar 16^th, 2014, 6:05pm By: aaron_do
recommended phase margin for VCO LDO	aaron_do	3	5656	Mar 14^th, 2014, 12:39am By: aaron_do
ADC Unit Capacitance	aaron_do	14	13295	Mar 7^th, 2014, 8:44pm By: carlgrace
SAR ADC input stage and speed limitations	aaron_do	0	2115	Feb 27^th, 2014, 5:24pm By: aaron_do
PLL reference spurs, and jitter vs phase noise	aaron_do	4	5965	Feb 24^th, 2014, 4:37pm By: aaron_do
Bond wire coupling	RobG	11	11961	Feb 18^th, 2014, 7:01pm By: loose-electron
RMSjitter contribution of chargepump to pll o/p. factor of 2 after integ or not?	yvkrishna	0	1513	Feb 13^th, 2014, 1:41am By: yvkrishna
pll chargepump o/p noise profile	yvkrishna	1	3295	Feb 13^th, 2014, 1:22am By: yvkrishna
SAR ADC decoupling capacitance	aaron_do	11	9157	Feb 4^th, 2014, 5:22am By: boe
Bootstrapped switch body tie	aaron_do	9	8705	Jan 15^th, 2014, 4:19pm By: loose-electron
ADC ENOB, SFDR, SNDR	aaron_do	2	4596	Jan 13^th, 2014, 7:03am By: aaron_do
MDAC settling time	aaron_do	7	6454	Jan 13^th, 2014, 12:24am By: aaron_do
how critical is the loop filter capacitor layout in a PLL?	aaron_do	8	1705	Jan 12^th, 2014, 4:53pm By: aaron_do
pipelined ADC MDAC	aaron_do	3	63	Jan 6^th, 2014, 9:38am By: carlgrace
SNR_max or Dynamic Range of Delta Sigma/Oversampling ADCs	harpoon	0	1612	Jan 6^th, 2014, 3:27am By: harpoon
First Order Delta Sigma - Cap sizing	harpoon	2	3129	Jan 3^rd, 2014, 1:18am By: harpoon
Sample and Hold	aaron_do	3	3699	Jan 2^nd, 2014, 4:30am By: sushan
Pipelined ADC without front-end SHA	aaron_do	3	4439	Dec 25^th, 2013, 9:01pm By: carlgrace
interpolation	aman gupta	7	5011	Dec 13^th, 2013, 10:14am By: boe

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