Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
VERILOG-A and imaginary numbers and functions	T-4444	2	5699	Oct 18^th, 2011, 11:04pm By: T-4444
accuracy of PSP and BSIM model in the Accumulation mode	aaron_do	2	5690	Sep 28^th, 2011, 6:14pm By: aaron_do
VHDL-AMS VBIC model?	the_pd	2	3474	Sep 19^th, 2011, 8:20am By: Geoffrey_Coram
TSMC 90nm/65nm/45nm/28nm Noise Factor	neoflash	0	3599	Sep 10^th, 2011, 10:55pm By: neoflash
IBM45nm (SOI ) technology Gate resistance problem	nadroit	1	3023	Jul 20^th, 2011, 6:36am By: Geoffrey_Coram
PSP 101.3 Verilog-A Model Problem	Mihir Mudholkar	5	6389	Jul 12^th, 2011, 10:33am By: Geoffrey_Coram
Does TSMC Spice model include impacted ionization effect?	neoflash	5	7157	Feb 1^st, 2011, 3:37pm By: neoflash
How are Vtlin and Vtsat extracted from simulation results	modelman	3	79	Feb 1^st, 2011, 3:24pm By: Mooraka
Information about Epitaxial layer	DoYouLinux	3	4915	Jan 31^st, 2011, 6:58pm By: modelman
Capacitance based model vs charge based model	kumar.g	4	5436	Jan 20^th, 2011, 6:45am By: c1000
Self-heating simulation	McSim	9	2163	Dec 27^th, 2010, 3:11am By: McSim
How are PDK's made?	somisetty	4	4515	Dec 1^st, 2010, 12:34am By: haykp
about breakdown voltage	rajesh14	2	4225	Nov 30^th, 2010, 7:11am By: Colbhaidh
How foundries make low vt mosfet	rfmems	5	6935	Nov 30^th, 2010, 6:48am By: Colbhaidh
Re: Snapback in LDMOS	ujwal	0	3123	Oct 11^th, 2010, 3:45am By: ujwal
Spectre BSIM3(V3.2) Model Questions	pink_panther	2	55	Sep 16^th, 2010, 7:32am By: pink_panther
pMOS gate capacitance	Godfrey	4	5204	Sep 3^rd, 2010, 2:09am By: Lex
poly resistor vs nwell for 1/f noise	rfcooltools.com	3	1066	Aug 18^th, 2010, 5:04am By: hande.vinayak
viarations of poly resisitor	kennycs	5	5965	Aug 7^th, 2010, 1:48pm By: love_analog
capacitance in device models	c1000	1	2533	Aug 5^th, 2010, 6:48am By: Geoffrey_Coram

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