Dear Ken:

I'm sorry to bother you again. I attempt to use SpectreRF extracting the jitter of an RF ECL divide-by 4/5 prescaler which operates at 4GHz, ie. its output freq is at 1GHz.
I follows the instructions in 9.1.1 of the paper(phase noise+jitter). I first perform PSS analysis, and I use Direct Plot to plot output voltage waveform. It showed a square-like wave with about 1Vpp, and the positive edge comes at 800ps on the plot. Then the slope around the threshold is counted to be 500mV/0.05ns=10GV/s. After that, I performs the PNoise analysis.

In the PNoise setup window, the sweeptype is chosen to be absolute, the "frequency sweep range" (start-stop)is set to be 1 to 1e9, and maxsideband is set to 8. And I Set Noise type to be time domain, fill the "Noise Skip Count" blank with 10e3, check the "Add Specific Points", and add 800ps in the blank. After the PNoise analysis is complete, I use "tnoise" and the function is set to "Integrate Noise". I think it counts for the variance of output noise voltage by the eq: integ(pow(getData("out" ? result "pnoise"))2), and the integration range is 0.5GHz to 1GHz. The square root of the result is 60. And I use eq(51) to compute Jee which is shown to be sqrt(2*60^2)/10G=8.4ns. However, this number doesn't not seem to be reasonable!

In eq(52), the var(nv(tc))=integral of Snv(f, tc) with the upper and lwer limts of +/-(0.5*f0). Since f0=1GHz, I thought at least the output noise voltage spectrum should be obtained first. So I set the PNoise sweep range to be 1 to 1GHz. When it comes to the integral of Snv. I'm not very sure how to integrate Snv with the range (-0.5GHz, +0.5GHz), therefore I considered the lower limit for the absolute type is 1GHz-0.5GHz=0.5GHz. And then I counts the integral of Snv over the range from 0.5GHz to 1GHz, and after that, I double the result to take the 1GHz to 1.5GHz into consideration. But unfortunately, that was totally wrong! ???

I thought I am not adept in Spectre, and I didn't know very well to setup my simulation to fit the environment described in the paper. I thought I misunderstood the meanings of many parameters in my testbench. Could you tell me what goes wrong in my testbench settings?

And, I'm wonder why we should simulate dividers in strobed-noise feature rather than contineous? The arguement is that only the noise around the threshold would dominate. If I simulate my divider as well as a VCO, what would be the difference? If we integrate all the noise over the contineous frequency domain, will the computed phase noise be wrose? ???

Dear Ken:

Thank you very much for your help. As you said, after I re-adjust my integration range to eliminate the sigularity point at 1GHz. The integrated noise voltage has been down to 1.4mV which resulted in a jitter of 0.14ps.

-Aigneryu