I've included a module I use to sample an output voltage and write it out to a file in SPW format. The Spectre pwlf sources understand SPW format but SPW format is not necessary. Two columns, one time and one voltage, works too. Perhaps this will get you started.

I did not make the filename a parameter because I know of no way to pass a string to the module. That is one of my complaints about VerilogA. SpectreHDL lets you pass strings to modules.

The other thing to remember is that if you post process the data on a pc, you need to rename the file with a different name each time you overwrite the old one because of some caching problem with pc networks. This is, of course, moot if you are doing everything on a unix box.

// VerilogA for behavioral_models, SPW_signal_sink, veriloga

`include "constants.h"
`include "discipline.h"

module I_SPW_output_sink(in);
input in;
electrical in;

parameter real sample_rate = 1e6 from (0:inf];
parameter real sim_time = 0.001 from (0:inf];
parameter integer record = 1 from [0:1]; // 1 = record, 0 = don't.
integer fptr;
real period;
integer number_of_samples;

analog begin
  @ ( initial_step ) begin
     if (record ==1) begin
        fptr = $fopen("/home/phase_noise.ascsig");
        period = 1/sample_rate;
        number_of_samples = sim_time*sample_rate;
        $fstrobe(fptr, "$SIGNAL_FILE 9");
        $fstrobe(fptr, "$USER_COMMENT");
        $fstrobe(fptr, "data");
        $fstrobe(fptr, "$COMMON_INFO");
        $fstrobe(fptr, "SPW Version          = 4.50");
        $fstrobe(fptr, "System Type          = solaris2");
        $fstrobe(fptr, "Sampling Frequency   = %g", sample_rate);
        $fstrobe(fptr, "Starting Time        = 0");
        $fstrobe(fptr, "$DATA_INFO");
        $fstrobe(fptr, "Number of points     =        %d", number_of_samples);
        $fstrobe(fptr, "Signal Type          = Double");
        $fstrobe(fptr, "$DATA ASCII");
     end
  end

  if (record == 0) period = 1e6;
  @(timer(0, period)) begin
     if(record == 1) $fstrobe(fptr, "%g", V(in));
  end

  @ (final_step) begin
     $fclose(fptr);
  end
end
endmodule