In a book , it says ESD pulses applied to a bounding pad may come in different formats, such as PD(positive ESD stress from I/O pad to VSS), ND, PS, NS DS (positive ESD surge from VDD to VSS)mode. An ideal ESD protection  scheme for an pad should be able to protect the pad against ESD  transients of all the modes. I can not understand this. For example, if a positive pulse is applied to the pad, and the circuit has a protectin unit that can form a low-impedance shunting path to the VDD, then the circuit is protected. I think it is no use to have another low-impedance shunting path to the VSS. So in my opnion, I think an ESD protection scheme which can protect the pad against ESD transients of PD,ND, DS mode or PS, NS, DS mode is enough.

  my second question is, in a book , it says "to qualify
for whole-chip ESD protection, there must exist a low-impedance conducting channel, preferably in active mode, from each pad to any other pads on a chip."
I think this is not necessary.

  who can answer my question?