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help on the CADENCE ahdl lib (Read 8884 times)
Aigneryu
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help on the CADENCE ahdl lib
Jul 08th, 2003, 1:35am
 
Hi !

I have some problem in using ahdl library. I need to sample the
voltage wave and put the sampled points (discrete numbers) to another file. But when I use the "sampler" block in ahdl lib, it doesn't work. I specified the sampling time and filename.
Bit I can't find where the saved file is, and it seemed that no new file was created.

Where can I get the guide to use the ahdl lib provided by
Cadence IC?

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Andrew Beckett
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Re: help on the CADENCE ahdl lib
Reply #1 - Jul 9th, 2003, 5:10am
 
The filename argument is only used if you simulate using
the spectreHDL model (the ahdl view). If you pick
the veriloga view instead, then it writes out the filename
as %C:r.dat (which means root of the input file name with
.dat added). So since the input file under ADE will be
input.scs, the resulting filename will be "input.dat",
and will be created in the directory that the simulation
is run in, which will be:

<projectDir>/<cellName>/spectre/schematic/netlist

Now you may find that the file appears to be empty still.
This is because there's nothing to flush the file at the
end of the simulation if you're running spectre in
"interactive" mode (which is the default through ADE).
There's a PCR for this, but in the mean time, doing
a Simulation->Stop or setting:

Code:
envSetVal("spectre.envOpts" "controlMode" 'string "batch")
 



in the CIW or .cdsinit before starting ADE should fix that.

Note, I found the location of the file purely by
looking at the model code - which you can do too.
I suppose you need to know the directory it ran
in, but you have that info now!

Regards,

Andrew.
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Aigneryu
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Re: help on the CADENCE ahdl lib
Reply #2 - Jul 10th, 2003, 1:08am
 
Thanks

But when I check my default simulation directory
there are two folders, spectre and spectreVerilog

In fact, I run the simulation with spectreVerilog and config view
I  found an input.scs is in ~/spectreVerilog/config/netlist/analog

According to the given comment, I should find the dat file whether this file is empty or not. However, there is no such file there.

What probably the problem is?
Could my environment setting be wrong?
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Andrew Beckett
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Re: help on the CADENCE ahdl lib
Reply #3 - Jul 11th, 2003, 2:13am
 
I just tried this with spectreVerilog, and the input.dat
file got created in the <projectDir>/<cellName>/spectreVerilog/config/netlist/analog
directory.

I'm assuming in your config you're selecting the veriloga
view of the sampler? If you're using the ahdl view, then
if the filename is a relative path, it will be created
in the netlist dir (which is where the simulation is run from).

I did this in IC50 - but I'd be very surprised if it was
different in any other version - I doubt any of this
has changed in several releases.

Regards,

Andrew.
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Aigneryu
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Re: help on the CADENCE ahdl lib
Reply #4 - Jul 12th, 2003, 6:34am
 
Much thanks

I eventually found the .dat in that folder.
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