The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 16th, 2024, 3:07pm
Pages: 1
Send Topic Print
PLL Phase noise Simulations Vs Measurements. (Read 790 times)
dadir
New Member
*
Offline



Posts: 2

PLL Phase noise Simulations Vs Measurements.
Sep 19th, 2003, 12:46pm
 
Here is my story:

I designed a PLL (fo=800MHz)  in 0.13u digital process and got it fabricated. Then I measured the PLL output spectrum using a spectrum analyzer to get L(f). I decided to simulated the PLL in Spectre and compare the measured result. Using the device models I simulated the Phase noise of VCO, dividers, etc and volatge  noise of loop-filter, regulator etc... The VCO is a simple inverter chain running on a on chip regulated voltage. The regulator is between loop-filter and VCO. I calculated the phase transfer functions from various nodes to the PLL ouput and obatined the expected PLL phase noise output plot.  I noticed that when the PLL bandwidth is set to a very low value (100KHz ), almost all the phase noice is from the VCO, But there is a shift of 15dBc ( factor of 32) everywhere from 100k to 50Mhz bewtween measured and simulated specta. Measured one being higher. The shape of the spectrums are exactly the same but for the shift of 15dBc. This implies the simulated and measured phase noise spectra of the VCO are off by 15dBc. I am not able to account for this broadband noise source in my simulations. I have the following questions, any answer or suggestuion is appreciated

1) What could be the reason for error of 15dBc between simulated and measured PLL phase noise spetra?

2) When I simulate VCO in spectre and plot the phase noise does it give phase noise directly or do I have to multiply by a factor of 2 to get the phase noise (Sphi)?

3) Under what conditions can I equate L(f) to Sphi?
Since flicker noise of the NMOS (used in VCO) in my process contributes to most of the noise till 40-50MHz. The flicker noise corners for NMOS is quite high (130Mhz) as compred to PMOS (2MHz), which were used in the VCO.

4) I suppose the spectrum analyzer measures L(f). Under what conditions can I equate L(f) (measured by spectrum analyzer) to Sphi? It is right even if the flicker noise is the major contributer to the phase noise?

5) Do I have to normalize the spectra measured by spectrum analyzer  before I compare the measured and simulated spectra? I read in some papers that the Total integral of L(f) should be equal to 1.

6) If I want to include phase noise contribution of the VCO and its regulator should I have simulated VCO and regulator seperatly or can I simulate VCO+regulator as one unit? Or it dosen't matter?

Thank you ver much.
Back to top
 
 
View Profile   IP Logged
Paul
Community Fellow
*****
Offline



Posts: 351
Switzerland
Re: PLL Phase noise Simulations Vs Measurements.
Reply #1 - Sep 23rd, 2003, 6:57am
 
Hi Dadir,

I'm not an expert in phase noise in PLL's, but allow this stupid question:
may the factor 32 come from the effect of the divider which you might have forgotten in your calculations?

Good luck,

Paul
Back to top
 
 
View Profile WWW   IP Logged
dadirr
Guest




Re: PLL Phase noise Simulations Vs Measurements.
Reply #2 - Sep 23rd, 2003, 10:42am
 
Hi paul,

        I don't have a /32, or /16. The vco frequency is 800Mhz and ref clock is 400MHz. I have divide by 2 in the
feedback path.  And if BW is set to very low value most of the pnoise at PLL output is VCO pnoise, which is not effected by divider value.

Thanks
dadir
Back to top
 
 
  IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.