Hi,

I'm working on a 10-bit 100Msamples/sec Pipeline ADC in CMOS. The architecture is 1.5bit/stage with a front-end SHA. Each stage is essentially a switched-capacitor gain block. I would like to use the Pnoise analysis to predict the output-referred noise contribution of a single stage. However, I am not sure how to interpret the results I am getting. Having read Ken Kundert's papers, should I :
(a) use an ideal SHA at the output of the stage with the sources option in the Pnoise setup or,
(b) use the tdnoise option in the Pnoise setup and specify the sampling instant as the time of the falling edge of the sampling phase?

In both cases I am unsure what range of freq to integrate over because the output of one stage will be sampled by a next stage, which will in turn add noise and again cause folding of the noise into the baseband. The cct uses two non-overlapping phases of a 100MHz clock. A figure of merit for an individual stage would help me scale the stages appropriately down along the pipe!

I would really appreciate any help, tips, ideas or opinions,
Regards,
Pieter  ???