Hi George,

for NMOS, the substrate is a p-type. for PMOS, the substrate is a n-type. the substrate of NMOS and PMOS can form a parasitic diode, which is undesired.

therefore, in order to reverse bias the diode, the anode voltage of the diode should be lower than the cathode.

Hence, the substrate of NMOS is connected to the min potential, which is in this case a gnd or -vss.

Rgds
Edward

Hi George,

you should find out if your technology provides triple well or not. If so, the standard cells may be used with body biasing techniques to reduce leakage currents. In that case you can have different voltages on both nodes.

If the NMOS devices are in common substrate (not in a well), you must apply the same voltage to both nodes, as mentioned by Edward. Connecting it on-chip or off-chip is part of a global substrate noise reduction technique which you should consider for each design seperately. In order to avoid body effects, I would in most cases recommend to use the local NMOS source voltage to connect the substrate.

If you have substrate noise problems, use additional independent guard rings to pick it up. These should be connected to a seperate supply pin and only be taken to GND off-chip.

Paul

The substrate has to be connected to the same ground node as the source if, say, the NMOS/PMOS is used in current mirror.  On the other hand, if the internal ground bounce of a digital part is severe that a separate and more silent substrate ground will reduce the injection of noise into the substrate.