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sim Junior Member Offline Posts: 11	[need help] veilogA design flow Mar 05^th, 2004, 1:07am Who can give a detail design flow for analog hardware language ?(In Cadence design enviroment).thanks!
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Andrew Beckett Senior Fellow Offline Life, don't talk to me about Life... Posts: 1742 Bracknell, UK	Re: [need help] veilogA design flow Reply #1 - Mar 5^th, 2004, 1:36am Have you tried reading the documentation first? Your question is rather open-ended... Andrew.
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sim

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Re: [need help] veilogA design flow
Reply #2 - Mar 8^th, 2004, 9:36pm

CaXXXXX documents are hard to read for fresh man. Cry

maybe,caXXXXX want to do this: If you don't pay money to us,you can't use my software well.

but i'm a student,i have no money ,i have to use their tools from �other pass............ �

I have read the following doccuments :
Affirma Verilog-A language reference
Verilog-A Debugging Tool User guide

they �contain less demos and flows. troublesomely,i can't
build the design concept. I want to get the ideals from senior designer, and I can study Verilog-A more efficiency .

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sim Junior Member Offline Posts: 11	Re: [need help] veilogA design flow Reply #3 - Mar 8^th, 2004, 9:47pm Who can give me a lab for CadXXXX verilog-A design flow? thank a lot!
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Andrew Beckett

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Re: [need help] veilogA design flowpllLib &
Reply #4 - Mar 8^th, 2004, 10:03pm

Well, a quick reply from somebody who works for the
company who offends you so much (given the XXX's in your
postings).

There is a Quick start tutorial for AMS Designer:

<instdir>/tools/dfII/samples/tutorials/AMS

look at the README there.

If you want starting places for models, then try looking
at the "modelwriter" tool, as well as the following sample libraries
in the installation:

Code:

ahdlLib	   $CDS_INST_DIR/tools/dfII/samples/artist/ahdlLib
rfLib	     $CDS_INST_DIR/tools/dfII/samples/artist/rfLib
pllLib	    $CDS_INST_DIR/tools/dfII/samples/artist/pllLib
bmslib	    $CDS_INST_DIR/tools/dfII/samples/artist/bmslib

The last of these (bmslib) was only added in the IC5033
release.

You may also benefit from going through the
Cadence Analog Design Environment User Guide
(not a tutorial, but pretty comprehensive).

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Eugene

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Re: [need help] veilogA design flow
Reply #5 - Mar 9^th, 2004, 9:35am

sim,

Are you asking for a general idea of how analog behavioral languages fit into a design flow or are you asking for a detailed example of a design project that used an analog behavioral language? You will have trouble getting the latter because such details are usually proprietary. However, if you are asking for the former, I can tell you how the language fits into a design project (ideally) and refer you to a book that gives examples of specific circuits.

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sim Junior Member Offline Posts: 11	Re: [need help] veilogA design flow Reply #6 - Mar 10^th, 2004, 1:30am to Andrew thanks a lot! to Eugene Can you commend some books to me?Waiting for your guidance.
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Eugene Senior Member Offline Posts: 262	Re: [need help] veilogA design flow Reply #7 - Mar 10^th, 2004, 1:17pm The only book I know of is "Analog Behavioral Modeling with the Verilog-A Language", by Dan Fitzpatrick and Ira Miller. Kluwer Academic Publishers. It gives several good examples but my one complaint is that it is not indexed very well. Were you also interested in basic design flows that use VerilogA/AMS?
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Andrew Beckett

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Re: [need help] veilogA design flow
Reply #8 - Mar 10^th, 2004, 2:00pm

The Fitzpatrick/Miller book also contains a number of
deviations from the Verilog-A standard, given that it
was written before the standard was finalised (before
the initial version even) - so watch out.

However, for covering general principles, it's a good
start - you may find that the syntax and names of
some tasks/functions and so on may have changed (I
don't recall exactly what; it's some time since I last
looked at the book).

Regards,

Andrew.

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sim

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Re: [need help] veilogA design flow
Reply #9 - Mar 10^th, 2004, 6:14pm

Eugene and Andrew Beckett
thanks for your help!I will find the book you refer me .

I want to search some articles and books that tell me how verilogA/AMS can be best used. step by step learn to build behaviror circuit model is perfered.

Eugene,pls tell me your basic design flow.Compared with yours, I can find some mistake in my flow.

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sim

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Re: [need help] veilogA design flow
Reply #10 - Mar 10^th, 2004, 6:46pm

Andrew
Question 1:
Can I write script to do SpectreVerilog simulation directly?
For example: �
circuit � � � � � � � � � language � � � �simulator
analog part-------verilog-A------- spectre
digital �part-------verilog � �------- verilogXL

Question 2:
Spectre simulation is carve up to direct simulation(spectre) and socket simulation(spectreS),why ?
it's hard to use,because it �take me many time to learn it.
which tool can convert spectre MOS model to SpectreS MOS model?

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Eugene

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Re: [need help] veilogA design flow
Reply #11 - Mar 10^th, 2004, 10:13pm

Sim,

I use VerilogA several places in a design flow. The first two ways I use VerilogA are in the applications that CAE sales people always describe. However, I use VerilogA more often in the other applications I list below.

1. Top down design: Most designs can be partitioned into function blocks. I use a spreadsheet to take the first crack at specifying the parameters for each function block. I then write behavioral models of each function block and simulate the performance of the overall system to check the spreadsheet. Sometimes I streamline the process by writing visual basic functions that automatically write out parameter files that the VerilogA modules read with an "include" statement. Some of my associates use VerilogA to write functional models instead of performance models. Functional and performance models are not necessarily the same. For example, a functional model of an RF amplifier might only have one input and one output. A performance model of the same amplifier might be a baseband equivalent model which as two inputs and two outputs because the baseband representation of a real RF signal is a complex signal. The performance amplifier model simulates noise and saturation. The functional model is too slow to simulate the time scales of interest but unlike its performance counterpart, the functional model makes sure the amplifier is connected properly.

2. Bottom up verification: Suppose you have a device level model of a function block and you want to see how it performs in the larger system but the larger system is to complex to simulate at the same level of detail. You can model the testbench behaviorally with VerilogA while leaving the device of interest at the device level and save in simulation time.

3. Golden models: This is perhaps one of my more frequent applications. I need to write a model in MatLab or C. I usually start from my library of VerilogA models because I can check VerilogA models in circuit level test benches. I generate test vectors to help debug the translation into MatLab or C. In this mode, the VerilogA model is a golden model that brigdes the gap between the higher level model and the circuit model.

4. Diagnostics: I can't tell you how many times someone has come to me with an set of annoying symptoms observed in the lab and a long list of hypothesized root causes. The proper course of action of course depends on a correct diagnosis of the symptoms. The real issue is that the system is either a chip with no test points, or a sealed box with months of successful testing under its belt that no one wants to void by breaking the seal. The only way to test the various hypotheses is through modeling and simulation. Behavioral modeling can help focus your efforts by simplifying circuitry that is not under suspicion and by importing lab measurements directly into the simulation. For example, you can fit a curve to I-V measured data to model a device more accurately than any simulator primitive model. I suppose this is a kind of bottom-up verification. However, I differentiate it from what the CAE vendors call bottom-up verification because it rarely feels like the scheduled task the CAE sales people describe. This task is never scheduled. This task is usually done with an acute sense of urgency imposed upon you by your entire management chain.

5. Test Definitions: You are in the early stages of a design; you are specifying something that does not yet exist. Sometimes, the parameters you specify can not be directly measured. In this case, you can use behavioral modeling to translate your theoretical parameters into easily measured parameters by simulating a test.

6. Customer support: I only come across this one once or twice. You have a potential customer who wants to simulate your product in his system before he buys; he wants a test drive. You do not want to give him your detailed model because you then expose your intellectual property. Instead, you provide a behavioral VerilogA model that simulates the specifications, and perhaps then some, but does not expose the details of how you achieve those cool specifications.

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Andrew Beckett

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Re: [need help] veilogA design flow
Reply #12 - Mar 10^th, 2004, 10:41pm

Sim,

To answer your two questions:

Quote:

Question 1:
Can I write script to do SpectreVerilog simulation directly?
For example:
circuit language simulator
analog part-------verilog-A------- spectre
digital part-------verilog ------- verilogXL

Well, running spectreVerilog from the command line isn't that easy. It can be run from within the analog design environment easily enough, and I guess you could write an OCEAN script to do it from the command line, but if you're unfamiliar with the tool, start off with doing it interactively.

The reasons for this is that this is a two simulator approach. The ADE environment will partition the design into two netlists (based on which parts need to be in which domains), and so any change of the partitioning requires a whole new netlist.

You need to start off by using the hierarchy editor to create a "config" view, which tells the netlisters which views are to be used for which blocks - and then you simulate using the config view in ADE.

I can't really go through the whole flow here - it's in the documentation (I'm sure) - but once you've got it all set up, then you could write out your session as an OCEAN script, and then it could be run in batch mode.

Alternatively you might want to consider using AMS Designer (I pointed at a tutorial for that in an earlier post) as this is a single simulator approach, and (in my opinion) considerably easier to use, especially if you're going to want to be able to use it standalone.

Quote:

Question 2:
Spectre simulation is carve up to direct simulation(spectre) and socket simulation(spectreS),why ?
it's hard to use,because it take me many time to learn it.
which tool can convert spectre MOS model to SpectreS MOS model?

There are two interfaces to spectre in the Analog Design Environment. spectreS is the older (obsolete) one, and spectre is the newer one. In the past, all simulators were integrated into ADE via what was called the "cdsSpice Socket" (the S at the end of spectreS comes from "Socket"). The reason that this was done was that many simulators did not have a rich language which supported parameterisation, at least not in a consistent way. So, what happened was that with spectreS, netlists were created using cdsSpice's language and then cdsSpice would handle all the parameter evaluation, and would spit out a "final" netlist with all parameters expanded for spectre to simulate. cdsSpice is not a terribly capable simulator, but it had a flexible front end preprocessor.

Now, as you can imagine, having a second tool in the way was hardly optimal - every time you changed a parameter it had to completely recreate the netlist for spectre. Also, it tended to make each simulator look like a basic spice simulator, and it was hard to access the full capabilities of the simulator.

So, back in IC443, a new "spectre" (direct) interface was added. In this case, ADE generates a native spectre netlist in spectre's own language, which is parameterised. spectre itself takes care of evaluation of the netlist. Also, ADE talks to spectre interactively, and this allows parameters to be changed without needing to restart the simulator or to recreate the netlist - so doing things like parametric sweeps, and quick parameter changes, are much much quicker. All the model files are in spectre's own syntax (although it can handle spice syntax models too).

So, if you have a choice, I'd go for spectre. There's really little point in trying to use the spectreS interface if your design kit supports spectre. spectreS is somewhat frozen; none of the new analyses since IC443 have been added to spectreS, just to spectre.

There's no real need to convert spectre models to spectreS, because you can specify include files in spectreS to be in spectre syntax instead of cdsSpice syntax (this is on the setup->environment form in spectreS).

Regards,

Andrew.

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sim Junior Member Offline Posts: 11	Re: [need help] veilogA design flow Reply #13 - Mar 11^th, 2004, 8:44pm I really appreciate your help! Eugene, it's a full-scale description! Andrew, I agree with you. I think the trend of mixmode simulator is single engine,that 's say,spectreverilog is used in transistion phase.
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