Eugene
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I see two possibilities but I have never tried them.
(1) There is a "delay" element in VerilogA but I do not know if the delay can be a dynamic variable. If it can, you will have to add thetamax to the sinusoid so that you do not request a negative delay. (No non-causal elements allowed.)
(2) Perhaps you could create a PLL that tracks the XMHz clock. Then add a sinusoidal perturbation to the VCO input. If you get the scale the sinusoidal source correctly, I think the VCO should dither sinusoidally about the XMHz clock as desired.
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