Hello,

I am designing a 10-bit 40MSamples/s pipelined ADC. Would you please tell me any references for voltage reference buffer?

I mean the buffers that drive Vref+, Vref-, Vcmo. Because its capacitor load, there must be enough output current to sustain the voltages stable. But that needs large quiesent current. Who has any ideas about the design of the voltage reference buffer? Thanks in advance.

Best regards,

Yawei Guo