There seems to be general agreement in the literature that a PFD has a dead zone around small phase errors. I've measured PFDs down to 100ps phase error, and using SPICE have gone all the way down to 10fs phase error, with no loss of linearity, and no dead zone.

Does anyone who believes in the dead zone have a concrete example demonstrating its existence? I'm particularly interested in measured results or real circuits in the published literature, and far less interested in the junk published in most application notes, which generally states that a dead-zone exists, offers a solution, then shows that using the solution there's no dead zone. My solution doesn't have a dead zone either, but in my case, there never was one to begin with...

Quote:


That's what you'd think, but it's not what happens. Consider the case of an ECL PFD with an RC response and a negative phase error at the inputs. The UP output will rise to Vp(-1+2(1-exp(-(Tw+Tp)/tau))) then decay with time constant tau. The DN output will begin Tp later and will charge to Vp(-1+2(1-exp(-Tw/tau))) before beginning to discharge. Tw is the time UP and DN are both on, tau is the RC time constant, Tp is the phase error, and Vp is the peak output voltage. This is a resonably good model for an ECL PFD.

By choosing Tw and Tp to be small values, the PFD output can be given any desired peak amplitude. For example, choosing tau=1ns, Tw=300ps, and Tp=100ps, the peak values of the UP and DN outputs are limited to approximately -72mV. Assuming the thermal voltage of a diff pair, Vt, is 25mV, the diff pair in a charge pump input will only have switched 5.3% of its current, yet the charge pump output is still linear.

Here are the results of a Mathcad model of these equations. For each Tp, I integrate the charge pump output to get the total charge transferred to the loop filter.

Tp (ns)	Charge Transferred (fC)
---------	--------------------------
0.00001	0.00019364
0.00003	0.00058096
0.0001	0.001937
0.0003	0.005814
0.001	0.019
0.003	0.059
0.01	0.2
0.03	0.636
0.1	2.617
0.3	13.676
1	98.066
3	322.108

If you plot this data on a log-log plot, you'll find that it's remarkably linear, even down at 10ps phase error, and even though only 5.3% of the current is being switched at 10ps phase error. There's little point in going to smaller phase errors, since the charge transferred at 10ps is only 1.2 electrons. I suppose an argument could be made that there's a dead zone for phase errors that result in less than 1 electron transferred, but I think that's different than what we're discussing here.

Some nonlinearity shows up for errors larger than 1ns, but that's a different effect.

The primary problem with this example is that the UP and DOWN pulses are unlikely to only reach -72mV. They have to stay on long enough to generate the flip-flop reset pulse - the 0.3ns width used here, with the resulting -72mV maximum output, isn't wide enough to acomplish that goal. As Tw is made wider, the maximum output gets wider, and linearity should improve, although there's not much room for improvement. There isn't any practical possibility that Tw could be smaller. Of course, scaling the values to reflect a faster or slower process doesn't change the fundamental result.

I have simulated similar results on real circuits, and measured real PFDs in the lab, all with similar results.

-- Mike --

[quote author=Jitter Man  link=1085897049/0#3 date=1086111951]I believe that PFDs in ECL and other current steering logic families are not subject to deadzones. They are more common in other types of logic.
[/quote]

Okay, why do you believe that? Can you give an example of a PFD with a dead zone, in any logic family?

Mike

[quote author=Frank Wiedmann  link=1085897049/0#5 date=1086248985]If the PFD is realized in CMOS logic and the amplitude of the very narrow pulse falls below the switching threshold of the following stage, you will definitely have a problem. [/quote]

Well, sure, except that:

A. The switching threshold is only a hard fixed value in digital simulators and specialized circuits. In logic circuits, certainly in those used in PFDs, it's a transition region. My example above was for ECL, showing that the input signal doesn't have to get anywhere near the 0V "switching threshold" for the charge pump to respond. I think a similar case could be made for virtually any logic family.

B. If the amplitude is so small that it can't register in the charge pump, how did it ever get so large that it could switch the AND gate and turn off the PFD flip-flops?

I suppose you could mix and match logic families or go through other contortions to create a dead-zone, but that's not typically done, and the obvious solution in that case would be to fix the design.

Mike

You can find a circuit simulated in Hspice showing the existence of deadzone in the book
 "CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration" by Bram De Muer and Michiel Steyaert (Section: 6.8 )

The effect is very simple and could exist indeed. It exist only with combination of the phase/frequency detector and the charge-pump circuit.

The effect is as follows:

If the minimum pulse time of the phase/frequency detector is less that than the rise/fall time of the charge pump, the current could not settle up to the maximum value. So the charge integrated over one reference period is less than proportional to the pulse time of the phase/frequency detector output. The gain of the combination of both circuits is therefore reduced at the zero crossing. It is not truly deadzone but reduced gain depending on the ratio of the minimum pulse time to the rise/fall times.

The nonlinerity has the further effect that the noise shaping of a sigma-delta synthesizer is folded down.

Hi,

on that topic I would say its not only the PDF but also the CP who needs to be taken into account. The general solution is to have enough overlap on up and dn pulse in case of near-zero phase error, and two make the minmum width in this condition large enough that the CP internally also can work well with them. This needs to be checked carefully vs temperature, technology corners, etc. Best run also a MC analysis at WC conditions.

Bye Stephan