First, there is a qualitative difference between Spice, which is a simulator, and Verilog-AMS, which is a language. Verilog-AMS is read by mixed-signal simulators, such as AMS Designer from Cadence.

Spice accepts Spice netlists, which is a description of a circuit made up of interconnected components where the models of the components are hard coded into the simulator. Verilog-AMS is a language that can both describe the circuit as a netlist, and can describe the models for all of the components. Thus, this is another important difference. With Spice, you are constrained to use the models provided with the simulator, whereas Verilog-AMS allows you to describe any model.

Verilog-AMS is a relatively relative newcomer compared to Spice, and as such, many standard models are not yet available in Verilog-AMS, or available in a relatively immature state. This should change over time.

Finally, Verilog-AMS is a mixed-signal modeling language built on Verilog-HDL. As such, Verilog-AMS supports logic modeling, and digital and analog event driven modeling in addition to analog continuous time modeling. Spice only supports analog continuous time modeling.

The current trend is for Spice-level simulators to be combined with other simulators to form more powerful and flexible packages. Consider Spectre. Some time ago it added support for Verilog-A, added support for RF simulation, and was integrated into AMS Designer (a mixed-signal simulator). Thus, in the future, the distinction between Spice and Verilog-AMS will fade. You will eventually buy a simulator and it will support both Spice netlists and models, and Verilog-AMS.

Until then, you will need a Spice simulator for transistor level design. You will need an AMS simulator that supports Verilog-AMS if you are designing complex mixed-signal systems.

-Ken