rf-design
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Reiner Franke
Posts: 165
Germany
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I tried do catch up some informations about the technology but got nothing. I guess that they take a netlist and analyse how to separate the circuit. If the signal flow, analysed from the netlist, could be figured out as an directed tree then they could break up the netlist and simulate separate pieces. I am not shure that all supported simulators accept PWL sources for the interconnection signal flow with very high number of points.
This approach is similar to sparse matrix ordering methods but the difference is that from the netlist information you only know what is I, O or IO. And this categorisation is seldom true for analog.
So wait 14 days. Then they should leak some information.
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