It is stated that the large signal stability condition is satisfied if the rising slope of the ramp is higher than the rising slope of the voltage ripple just before the comparator.
I wonder if the above is not satisfied, are we able to see the oscillation in simulation ? assuming we are using cadence spice tool.
Thanks !

Eugene,
 It looked very similar to the subharmonic oscillation as in the current mode converter.
 But when I asked someone senior in my company about voltage mode converter, the oscillation due to the higher gain of error amp and output slope (compare to the ramp signal), is more of theory and is rarely seen.
 However, I get to read about it in many articles (design articles), which would not dig too much about it, but seems like a requirement in the design procedures.

Thanks.