Boon-siang,

   Have you tried using nchelp? If I remember the syntax
it is

  nchelp ncsim RNAERR from the command line.

Nchelp usually provides a  pretty good explanation of
the problem.

                                                     Best Regards,

                                                        Sheldon

Sheldon or anyone who is able to help,

After fixing that error, another problem came around. After running DesignPrep to get my design's verilog netlist. I noticed that there's something wrong with it. I have tried it on 2 accounts. One of the account works and the other doesn't because both account generated a slightly different verilog netlist. I had tried searching for any misconfiguration and tried copying the settings of the account that works to the one that doesn't but still with no prevail.

Below is a verilog netlist generated from the NON-WORKING account:
----------------------------------------------------

// Verilog-AMS netlist generated by the AMS netlister, version 5.0.33.500.3.31.
// Cadence Design Systems, Inc.

`include "disciplines.vams"

module inv_ams ( Vout,vss,vdd,Vin );

output   Vout;
inout   vss;
inout   vdd;
input   Vin;


nfet #(.panw8(0p), .panw6(0p), .ps(1.525u), .panw10(0p), .plnest(-1),
.pam2(0p), .panw2(0p), .plorient(-1), .nrs(1.1064), .panw9(0p), .nrd(1.1064),
.as(1.24E-13), .l(160.0n), .rf(0), .panw5(0p), .panw7(0p), .pld200(-1),
.pd(1.525u), .panw3(0p), .dtemp(0), .pam1(0p), .nf(1), .ad(1.24E-13),
.ngcon("1"), .rf_rsub(1), .panw4(0p), .w(280.0n), .panw1(0p), .m(1))
(* integer library_binding = "cmrf8sf";
   integer passed_mfactor = "m"; *)
 T1 ( Vout, Vin, vss, vss );

pfet #(.panw8(0p), .panw6(0p), .ps(2.715u), .panw10(0p), .plnest(-1),
.pam2(0p), .panw2(0p), .plorient(-1), .nrs(1.1064), .panw9(0p), .nrd(1.1064),
.as(2.09E-13), .l(160.0n), .rf(0), .panw5(0p), .panw7(0p), .pld200(-1),
.pd(2.715u), .panw3(0p), .dtemp(0), .pam1(0p), .nf(3), .ad(2.09E-13),
.ngcon("1"), .rf_rsub(1), .panw4(0p), .w(280.0n), .panw1(0p), .m(1))
(* integer library_binding = "cmrf8sf";
   integer passed_mfactor = "m"; *)
 T0 ( Vout, Vin, vdd, vdd );

endmodule

----------------------------------------------------

If you noticed the ngcon (number of gate contacts) in both pfet and nfet is ngcon("1") but from the WORKING account it's ngcon(1). Hence, I manually removed the "" in the NON-WORKING account and I could invoke AMS simulator succefully. But, I cannot do this for all my design, it would be impossible. Anyone out there who can help me??

The error that I'm getting if I don't manually remove the quotations are shown below:

----------------------------------------------------

Updating snapshot thesis.inv_ams:ams1121398730741 (SSS), reason:  mixed-signal design
Update of snapshot thesis.inv_ams:ams1121398730741 (SSS) successful.
     Starting analog simulation engine...
           libpalermo:  @(#)$CDS: libpalermo  version  02/26/2004 03:08 (ncss17) $(sub-version  0226  )

Analog Kernel using -ANALOGCONTROL
       /nfs/ecsnas1/users/eegrad/bcheah/ibm13/sch.scs.

Error found by spectre during circuit read-in.
   inv_ams: Parameter expression for `ngcon' is not supported.

spectre terminated prematurely due to fatal error.
ncsim: *E,RNAERR: Simulation is complete, analog initialization error.

----------------------------------------------------

Please help. Thank you very much.

Boon-Siang

Andrew,

Thanks for the reply. That explains a lot. Both my accounts are accessing the same version of ibm 0.13 um technology but in a different path. I have 2 copies of the identical library installed on separate servers.

Where would look for to enable the parseAsNumber to "yes" for the ngcon parameter? Where would you suggest to look for the CDF parameter settings? or I'm not suppose to change it.

Thank you very much for your help.

Boon-Siang

Hi Andrew,

Thanks for the valuable knowledge. I solved my problems already. Thank you very much.

I do have another question. From my previous posting, I mentioned that my first problem was I was using global vdd and vss in my schematics and the generated netlist cannot be parsed into the simulator. I solved it by changing the global sources (vdd! & vss!) to vdd and vss. Is there any way around this because if there's an easier way for AMS to recognize global sources (which I think it should) rather having me changing each and every schematic in my design with vdd and vss. I'm thinking it must be my settings again.

It would be very helpful if you could help me out on this too.

Thank you very much.

Boon-Siang

Hi Andrew,

I'm sorry for not being clear with my question. I'm using inout pins as my vdd! and vss! in my schematics. When I simulate them with just spectre, they are fine. But when I uses AMS environment. I was getting the following errors:

---------------------------------------------------
ncelab: *E,CUCFUN: instance 'ams_alias_inst_0' of the unit 'cds_alias' is unresolved in 'thesis.reg15:schematic'.
ncelab: *E,CUCFUN: instance 'ams_alias_inst_1' of the unit 'cds_alias' is unresolved in 'thesis.reg15:schematic'.
ncelab: *E,CUCFUN: instance 'ams_alias_inst_0' of the unit 'cds_alias' is unresolved in 'thesis.dff:schematic'.
...

I noticed that my generated netlist have some of the 'cds_alias' generated as shown below:

----------------------------------------------------
// Verilog-AMS netlist generated by the AMS netlister, version 5.0.32.500.10.
// Cadence Design Systems, Inc.

`include "disciplines.vams"

module halfAdder2 ( A,S,Cout,\vss! ,\vdd! ,B );

input   A;
output   S;
output   Cout;
inout   \vss! ;
inout   \vdd! ;
input   B;


cds_alias #(.width(1)) (* integer library_binding = "basic";
integer view_binding = "functional"; *) ams_alias_inst_0 (\vss! ,
cds_globals.\vss! );
cds_alias #(.width(1)) (* integer library_binding = "basic";
integer view_binding = "functional"; *) ams_alias_inst_1 (\vdd! ,
cds_globals.\vdd! );

\or   (* integer library_binding = "thesis";  *) I3 ( .A( A ), .F(
net10 ), .B( B ) );

inv  (* integer library_binding = "thesis";  *) I2 ( .Vout( net9 ), .Vin(
Cout ) );
...

---------------------------------------------------

As I mentioned in the previous post, I solved it by naming my global vdd! and vss! as just vdd and vss for each design. But it's too much of a hassle to do that if I need to do it for all my schematics. Plus, I have re-wire most of my design in that case.

Yesterday, I found another way to get rid of the problem. I used the symbol of vdd and vss from "analogLib" library instead of creating my own pins. AMS generated the netlist without the "cds_alias" lines. It seems to solve the problem.

If you know of any other ways, please let me know. If any of these make sense to you, could you explain to me why this is happening?

Thank you very much. If you need any more information, I would gladly provide.

Boon-Siang

Hi Andrew or anyone,

I had fix my previous segmentation fault problem already. I fixed it by using LDV 5.1 instead of LDV 4.1. It seems that LDV 4.1 has bugs. But I did ran into another problem. I need help to write connect rule files. I tried the one given in the affirmaAMS library but it didn't help. I'm attaching the errors that I got and the top module (ideal_adc_13bits_test2) generated netlist.

Please help. I had been stuck with numerous problems for the past week already.

Thank you very muchl.

Boon-Siang

========================================================================

Elaborating thesis.ideal_adc_13bits_test2:config -
 ncelab thesis.ideal_adc_13bits_test2:config -snapshot ideal_adc_13bits_test2:ams1121348439832 -cdslib /nfs/ecsnas1/users/eegrad/bcheah/ibm13/cds.lib -hdlvar /nfs/ecsnas1/users/eegrad/bcheah/ibm13/hdl.var thesis.cds_globals:ideal_adc_13bits_test2_config my_connectrules E2L L2E -errormax 50 -discipline logic -timescale 1ns/1ps -noparamerr -use5x4vhdl -status -delay_mode None -novitalaccl -neverwarn -update -omicheckinglevel Standard -access +r-w-c
ncelab: 05.10-s021: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
net065 ), .bit5( net068 ), .bit12( net061 ), .bit2( net071 ), .bit11(
    |

ncelab: *E,CUVNCM (../thesis/ideal_adc_13bits_test2/schematic/verilog.vams,38|39): No connection module found:Need an input port of discrete discipline logic, and an output port of continuous discipline electrical.
net12 ) );
   |

......

ncelab: *E,CUVNCM (../thesis/ideal_adc_13bits_test2/schematic/verilog.vams,44|4): No connection module found:Need an input port of discrete discipline logic, and an output port of continuous discipline electrical.
ncelab: Memory Usage - 22.5M program + 112.8M data = 135.3M total
ncelab: CPU Usage - 11.3s system + 61.0s user = 72.4s total (90.7s, 79.8% cpu)
Error encountered during NC elaboration for configuration thesis.ideal_adc_13bits_test2:config.
========================================================================


========================================================================

// Verilog-AMS netlist generated by the AMS netlister, version 5.0.32.500.10.
// Cadence Design Systems, Inc.

`include "disciplines.vams"

module ideal_adc_13bits_test2 ( bit8,bit5,bit12,bit2,bit11,bit0,bit10,
bit3,bit6,bit9,bit7,bit1,bit4 );

output   bit8;
output   bit5;
output   bit12;
output   bit2;
output   bit11;
output   bit0;
output   bit10;
output   bit3;
output   bit6;
output   bit9;
output   bit7;
output   bit1;
output   bit4;

FIR  (* integer library_binding = "thesis";  *) I7 ( .in7( net066 ), .out4(
bit2 ), .in0( net073 ), .out12( bit10 ), .in4( net069 ), .in1( net072 ),
.out7( bit5 ), .out14( bit12 ), .out11( bit9 ), .out2( bit0 ), .out0(
net058 ), .out8( bit6 ), .in10( net063 ), .out5( bit3 ), .out10( bit8 ),
.in2( net071 ), .out6( bit4 ), .in9( net064 ), .in8( net065 ), .in5(
net068 ), .in12( net061 ), .out3( bit1 ), .in6( net067 ), .in3( net070 ),
.in11( net062 ), .out13( bit11 ), .Clk( net12 ), .out9( bit7 ), .out1(
net057 ) );

ideal_adc_13bits  (* integer library_binding = "thesis";  *) I6 ( .bit8(
net065 ), .bit5( net068 ), .bit12( net061 ), .bit2( net071 ), .bit11(
net062 ), .bit0( net073 ), .bit10( net063 ), .clk( net12 ), .bit3(
net070 ), .bit6( net067 ), .analogSignal( net9 ), .bit9( net064 ), .bit7(
net066 ), .bit1( net072 ), .bit4( net069 ) );

analogGen  (* integer library_binding = "thesis";  *) I4 ( .Vdd( net11 ),
.Vss( net10 ), .analsig( net9 ) );

clk_digital  (* integer library_binding = "thesis";  *) I3 ( .clk(
net12 ) );

endmodule

========================================================================

Quick suggestion, based on some limited research. It sounds as if the .pak file in the library thesis has got corrupted - I would try deleting the .pak file in that library, and recompiling.

Also, fix the multiple references to the same directory in your cds.lib file - perhaps that might be related?

If you can access sourcelink, solution 11177990 looks relevant.

Andrew.