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Disable timing check in NC-Verilog (Read 721 times)
ywguo
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Shanghai, PRC
Disable timing check in NC-Verilog
Oct 09th, 2005, 6:44pm
 
Hello,

I need to disable timing check for several instances on running post-layout simulation. The simulator is NC-Verilog.

Does anybody know how to disable timing check (setup time and hold time) for only several instances in NC-Verilog?


Thanks
Yawei
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ekne
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Yupp, I'm a viking

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San Diego
Re: Disable timing check in NC-Verilog
Reply #1 - Nov 4th, 2005, 9:41pm
 
Assuming you need to "remove" X propagation  :-/

NC-verilog
+ncnonotifier
still get the timing checks but no x generation due to timing checks.
perhaps together with +ncno_tchk_msg to suppress
the messages.

The +ncnotimingchecks disables all as you probably know.

//BEE
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