Hi Vivek,

that's an interesting topic. First I would like to discuss some points of disagreement.
a) ATE manufacturers nowadays offer high-performance modules for analog/RF testing. High-performance circuits are probably rarely tested on general purpose testers, although these mixed-signal extensions of course increase the test costs. For this reason, there is some ongoing research on BIST-type techniques for analog blocks (e.g. use DAC and ADC for mutual production test in CODEC circuits). You may find some interesting information on the following web site:
http://www.macs.ece.mcgill.ca/~roberts/ROBERTS/RESEARCH/TEST/Test.html

b) Regarding the test board traces, it is not prohibited to add a limited number of components (buffers, low-noise OPAMPS,...) on the test board in proximity of the DUT to improve the quality of the input signal, respectively the analog read-out.

Now to your converter discussion:
1) I disagree that low-bandwidth oversampled converters are simpler to test. First, INL and DNL may as well be specified for these circuits, which have higher resolution and thus need more samples to be acquired (increased test time). Second, due to the lower bandwidth, settling time is longer and especially in this field "time is money". Finally, for very high resolution converters, it may be impossible to verify the specified SNR on ATE.

2) Regarding clock jitter, I would guess most commercial designs include on-chip clock generation to guarantee a clean sampling clock and do not excessively rely on the external clock (to ease the customers application). As alread mentioned, INL and DNL probably require more test time in OS converters (due to the lower bandwidth) and should be measured in less time for Nyquist converter. These measurements shouldn't be too difficult either, because they are static.
Regarding DACs, analog read-out may indeed be an issue, but hoperfully Roberts' technique using the (usually available) on-chip ADC may help.

Finally, in these kinds of tests, it may be worth thinking about what specifications are guaranteed by design, i.e. more or less manufacturing and device parameter independent, in order to reduce somewhat the number of functional tests to be performed.

Looking forward to further discussion!

Paul

Hi Vivek,

here a couple of additional comments.
(1) For high-resolution converters, building a clean test board and environment to measure the real converter performance can be a head-ache. For this reason, I don't think a good signal generator, even with appropriate filtering, makes this test simple. Ground plane design, reference voltages, biasing etc are very critical. Of course, you can take care of all these factors, but it really isn't that easy.

(2) I believe the use of a DC servo loop would become much too time consuming, although code density test also requires quite some measurement time. The latter requires less hardware overhead though. I believe tonal behavior is design-dependent (and not so much device-parameter dependent) and should be determined during characterization, not during production test. Different noise sources in an ATE environment should add sufficient dither to suppress tonal behavior

(3) In the following reference, the authors explain how they first generate a high-precision ananlog stimulus using parts of the sigma-delta modulator of the DAC, but not its smoothing filter. Based on the assumption that the digital blocks, including the DAC modulator, are initially tested using digital BIST techniques, you can assume this signal to be correct. I'm not sure however in how far the assumption that the noise shaped by the DAC modulator is removed by the ADC's anti-aliasing filter is valid.
http://www.macs.ece.mcgill.ca/~roberts/ROBERTS/PUBLICATIONS/JOURNALS/1995/MADBIS...

Paul