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Behaviral modelling of dc-dc voltage converters (Read 637 times)
Jess Chen
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Re: Behaviral modelling of dc-dc voltage converter
Reply #15 - Mar 07th, 2006, 9:50am
 
Richard,

I e-mailed you my comments on the circuits you send me.

Regarding the switch model and canonical model, they are essentially the same in my opinion. The only real difference from what I can tell is that the canonical circuit always puts a reference node at the bottom of the schematic, which forces one to sometimes include a second DC/DC transformer or a frequency dependent controlled source.  However, Voperian's switch model does it with one, without having to introduce a zero in one of the controlled sources.

The only time I would be extra careful when using switch models or canonical circuit models is when you switch current into a capacitor that has a significant amount of ESR. For example, if the output capacitor of a boost converter has a big ESR, the canonical circuit's state space equations do not match the true state space averaged equations. However, the ESR must be fairly large to matter. I have not analyzed Voperian's switch model in that example but if I were to guess without doing the analysis, I would suspect it works like the canonical circuit. If I get a chance, I'll check. Theoretically, there's probably a dual problem with inductors but I suspect the dominant loss in most inductors is a series element, which is not the dual problem. For practical circuits, I think the switch and canonical circuit models should give the same results.

One key point is that if you are using a circuit simulator, you needn't linearize the circuit. As long as you have a time-invariant model, the simulator will linearize it for you. Also, you do not need to force everything into one canonical form. If you stick with the averaging basics, you can avoid introducing frequency dependent controlled sources that depend on operating point.

-Jess
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Jess Chen
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Re: Behaviral modelling of dc-dc voltage converter
Reply #16 - Mar 7th, 2006, 12:37pm
 
I forgot to comment on Bennett's book. Bennett's book appears to use the non-linear model that when linearized, produces the canonical model. I have to take a closer look at Voperian's model but I suspect there is not any significant difference.

-Jess
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Jess Chen
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Re: Behaviral modelling of dc-dc voltage converter
Reply #17 - Mar 7th, 2006, 1:51pm
 
If I understood Voperian's switch model, it has the same error as the canonical model with regard to capacitor ESR in a boost converter.  The problem is that the circuit model (canonical or averaged switch) does not capture the true state space averaged equations for this example. The boost converter with a bad capacitor is somewhat of an academic exercise but it does nonetheless reveal one advantage of VerilogA over macromodels. With VerilogA, I can model the state space averaged equations directly; I do not need to synthesize a circuit model of the equations. If I get a free weekend, I'll try to post a paper elaborating on this.

-Jess
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richard88
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Re: Behaviral modelling of dc-dc voltage converter
Reply #18 - Mar 7th, 2006, 3:03pm
 
Jess,
 Appreciate your answers.
 Do you mean you will post some examples on using verilogA to do the DCDC modeling ? That would be great !
 I am using Cadence as simulator, I wonder if it matters on the syntax and I also don't know how to run with VerilogA in Cadence.
 I catch a glimpse of Bennett's book, it has a model that incorporates DCM and CCM together. That's neat.
 I ran the ac sim with esr on cap, it seems to reflect correctly with a zero, I don't get why you have concern about the esr ?

Thanks.

Jess Chen wrote on Mar 7th, 2006, 1:51pm:
If I understood Voperian's switch model, it has the same error as the canonical model with regard to capacitor ESR in a boost converter.  The problem is that the circuit model (canonical or averaged switch) does not capture the true state space averaged equations for this example. The boost converter with a bad capacitor is somewhat of an academic exercise but it does nonetheless reveal one advantage of VerilogA over macromodels. With VerilogA, I can model the state space averaged equations directly; I do not need to synthesize a circuit model of the equations. If I get a free weekend, I'll try to post a paper elaborating on this.

-Jess

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Jess Chen
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Re: Behaviral modelling of dc-dc voltage converter
Reply #19 - Mar 7th, 2006, 4:20pm
 
Yes am going to try to post a paper but first I need to get permission from my employer to use their computers and Cadence licenses. I am somewhat surprised that I have not heard of any such papers or books yet. I spent many years modeling power supplies the way Bennett describes, with SPICE primitives. It's not easy. I have written many RF models in VerilogA but have not applied VerilogA to power electronics because I was into RF by the time any simulators supported it.

I did not read Bennetts approach to CCM and DCM mode in detail but at first glance, the schematics look like something me and a colleage published many years ago (see one of my earlier posts). Like Bennett, we also got many of our ideas from Dr. Bello, who Bennett mentions in his preface. We had gobbs of convergence problems. Perhaps Bennett's models are more robust. In any event, I think the VerilogA models will be fairly robust.

Regarding the capacitor ESR, it is a small affect, more of an academic problem. The ripple probably becomes the more serious issue before the modeling problem becomes noticeable. Afterall, they do call the basic assumption the "low ripple approximation". When the boost capacitor's ESR becomes large, so does the ripple.

-Jess
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richard88
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Re: Behaviral modelling of dc-dc voltage converter
Reply #20 - Mar 7th, 2006, 4:31pm
 
Jess,
 Why is modelling DCM important for the buck ? Esp ac model for DCM, I thought DCM is always one pole system and stable.
Thanks.


Jess Chen wrote on Mar 7th, 2006, 4:20pm:
Yes am going to try to post a paper but first I need to get permission from my employer to use their computers and Cadence licenses. I am somewhat surprised that I have not heard of any such papers or books yet. I spent many years modeling power supplies the way Bennett describes, with SPICE primitives. It's not easy. I have written many RF models in VerilogA but have not applied VerilogA to power electronics because I was into RF by the time any simulators supported it.

I did not read Bennetts approach to CCM and DCM mode in detail but at first glance, the schematics look like something me and a colleage published many years ago (see one of my earlier posts). Like Bennett, we also got many of our ideas from Dr. Bello, who Bennett mentions in his preface. We had gobbs of convergence problems. Perhaps Bennett's models are more robust. In any event, I think the VerilogA models will be fairly robust.

Regarding the capacitor ESR, it is a small affect, more of an academic problem. The ripple probably becomes the more serious issue before the modeling problem becomes noticeable. Afterall, they do call the basic assumption the "low ripple approximation". When the boost capacitor's ESR becomes large, so does the ripple.

-Jess




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Jess Chen
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Re: Behaviral modelling of dc-dc voltage converter
Reply #21 - Mar 7th, 2006, 5:01pm
 
Richard,

You're probably right about the system being more stable in the DCM but I'd still want to check it if my compensation network had more than two state variables. Furthermore, although stability is a key issue, it is not the only issue. If the bandwidth drops in the DCM, the audiosusceptibility, regulation, output impedance, and/or the input impedance could fall out of specification. If the converter can operate in the DCM these things should all be checked. For example, the supply may be required to respond to a transient load within some settling time. If the load goes from heavy to light such that the converter goes discontinuous, the transient response might be too slow. A state space averaged model that can change modes on the fly is very useful in studying such transients.

-Jess
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richard88
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Re: Behaviral modelling of dc-dc voltage converter
Reply #22 - Mar 7th, 2006, 5:31pm
 
Jess,
 Thanks for the explanation, it makes sense.
 I've emailed you with question on compensation network and some other questions again, hope you don't mind.
Thanks.

Jess Chen wrote on Mar 7th, 2006, 5:01pm:
Richard,

You're probably right about the system being more stable in the DCM but I'd still want to check it if my compensation network had more than two state variables. Furthermore, although stability is a key issue, it is not the only issue. If the bandwidth drops in the DCM, the audiosusceptibility, regulation, output impedance, and/or the input impedance could fall out of specification. If the converter can operate in the DCM these things should all be checked. For example, the supply may be required to respond to a transient load within some settling time. If the load goes from heavy to light such that the converter goes discontinuous, the transient response might be too slow. A state space averaged model that can change modes on the fly is very useful in studying such transients.

-Jess

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Jess Chen
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Re: Behaviral modelling of dc-dc voltage converter
Reply #23 - Mar 9th, 2006, 10:37am
 
Richard,

I responded to your e-mail. Please let me know if you did not receive it and I'll resend it.

-Jess
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Tommy
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Re: Behaviral modelling of dc-dc voltage converter
Reply #24 - Mar 20th, 2006, 8:56pm
 
Jess Chen wrote on Mar 7th, 2006, 1:51pm:
If I understood Voperian's switch model, it has the same error as the canonical model with regard to capacitor ESR in a boost converter.  The problem is that the circuit model (canonical or averaged switch) does not capture the true state space averaged equations for this example. The boost converter with a bad capacitor is somewhat of an academic exercise but it does nonetheless reveal one advantage of VerilogA over macromodels. With VerilogA, I can model the state space averaged equations directly; I do not need to synthesize a circuit model of the equations. If I get a free weekend, I'll try to post a paper elaborating on this.

-Jess


Mr. Chen,
Thanks. It will be really great if you post the paper.

-Tom
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #25 - Mar 21st, 2006, 1:23pm
 
I've seen some questions regarding how to implement a DC/DC transformer in VerilogA. Below is a netlist of a simple, poorly designed buck converter. I slapped the model together just to demonstrate the VerilogA model of the state space averaged switch, which I've also included. The model does not check for conduction mode or duty cycle saturation but it is a start. The netlist runs AC and transient analyses. The loop gain can be computed by taking the AC gain from the minus terminal of V3 to the plus terminal of V3. The phase should be interpreted as phase margin. If I can figure out how to insert an image, I'll add a schematic.

-Eugene

Code:
// Generated for: spectre
// Generated on: Mar 21 12:59:12 2006
// Design library name: Eugene
// Design cell name: buck
// Design view name: schematic
simulator lang=spectre
global 0
include "/tools/dfII/samples/artist/ahdlLib/quantity.spectre"

// Library name: Eugene
// Cell name: buck
// View name: schematic
V2 (net05 net018) vsource type=pulse val0=0.0 val1=1.0 period=10 delay=1p \
	  rise=1n fall=1n width=1
E1 (net050 0 net019 0) vcvs gain=1/2.0
E0 (net019 0 net012 net05) vcvs gain=-1000
V0 (net21 0) vsource dc=10 type=dc
V6 (net018 0) vsource dc=3 type=dc
V3 (net046 net050) vsource mag=1 type=dc
I5 (0 net19 net015 net046) DcDcX
R0 (net13 0) resistor r=1
R3 (0 net012) resistor r=10K
R2 (net012 net17) resistor r=10K
R1 (net17 0) resistor r=10
C1 (net19 net13) capacitor c=100u
C0 (net19 0) capacitor c=10u
C3 (net019 net012) capacitor c=100n
C2 (net17 0) capacitor c=10u
L0 (net21 net19) inductor l=10u
L2 (net015 net17) inductor l=1u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=25 \
    tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
    sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=100u write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
ac ac start=1 stop=10M dec=20 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
save L2:1
saveOptions options save=allpub
ahdl_include "/DcDcX/veriloga/veriloga.va"

 



Code:
//Written by Eugene, 3/20/06
`include "constants.vams"
`include "disciplines.vams"


//DC to DC transformer.
//For a buck configuration, connect gg to ground, iin to the
//input filter, vout to the output inductor, and dr to the
//voltage representing duty ratio.

module DcDcX(gg, iin, vout, dr);
inout gg;
electrical gg;
inout iin;
electrical iin;
inout vout;
electrical vout;
input dr;
electrical dr;
electrical intrn;
analog begin

// Note that I had to introduce an internal node, "intrn", to avoid a
// loop of rigid sources. i.e. replacing I(intrn,vout) with I(vout)
// produces a netlisting error associated with rigid loops.

   I(iin,gg) <+ I(intrn,vout)*V(dr);
   V(intrn,gg) <+ V(iin,gg)*V(dr);
end
endmodule
 



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richard88
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Re: Behaviral modelling of dc-dc voltage converter
Reply #26 - Mar 23rd, 2006, 8:56am
 
Eugene,
 I'm new to verilogA usage, could you explain what is (or how to use) "electrical intrn" ... sounds like electrical is a keyword.
 Also, do you have anything on Boost converter ? I hope to look into voltage mode, and subsequently on current mode.
 I have a boost converter configuration, can I email you offline to discuss with ?

Thanks,
Richard
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #27 - Mar 23rd, 2006, 4:12pm
 
Hi Richard,

"electrical" is indeed a key word. All inputs, outputs, variables, parameters, AND internal nodes must be declared. The "electrical intrn" statement defines an internal node that I use to sense output current without shorting the output pin to ground through the current probe and output voltage source.

I will try to assemble a boost converter during a lunch break. I should be able to simply rearrange the pins on the switch model.  

You can e-mail me at wb6mcc@aol.com.

-Eugene
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Eugene
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Re: Behaviral modelling of dc-dc voltage converter
Reply #28 - Apr 2nd, 2006, 12:49pm
 
I tried rearranging the circuit for a boost configuration, without changing the VerilogA model of the state space averaged switch. The boost model works fine in the time and frequency domains as long as there is no resistance in series with the main inductor. However, with just 100pOhms of resistance in series with the inductor, the circuit converges to the wrong DC operating point. If anyone's interested, I can post what I have. Otherwise I'll wait until I get around to fixing the series resistance problem.

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Re: Behaviral modelling of dc-dc voltage converter
Reply #29 - Apr 3rd, 2006, 8:50pm
 
Eugene,
Thanks for the code!This runs well in Cadence
I try to use the model with Silvaco tools. But I fail badly. The duty cycle input (net046) goes to over 800V!
I tighten all tolerence but no luck Sad

Pls let me know your thoughts.

Tanaka
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