I wrote one once in Verilog.. the logic of the sigma-delta modulator is quite simple..
for the PLL cases, I believe people most often have a semi-constant code "added" to the storage node on each
clock The carry bit of the adder is used to compare to the reference clock..
So for a div by 10.24 pll  you might use an 8 bit adder, and add 25  on each VCO cycle..
use the carry bit to compare with the reference..

- of course often one will divide the Output with a few stages of fixed division, so that the S-D can use simpler, low speed logic.
But the beauty of all the schemes is that its simple register operations, so the range of possible configurations is quite large.
of course there are a few that have nice noise properties etc..

hope this helps.