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Matching property of intra-metal cap (Read 500 times)
ywguo
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Matching property of intra-metal cap
Apr 29th, 2006, 11:25pm
 
Hi,

Though mixed signal process has very good MIM caps now, some designers use intra-metal caps (the parasitic cap between interconnections) to save a mask. Unfortunately, foundry rarely provides the mismatch report for their intra-metal caps. The paper by Roberto Aparicio and Ali Hajimiri on JSSC 2002, Capacity Limits and Matching Properties of Integrated Capacitors, explore various structures. The matching properties make me frustrate. The structure named VPP gets 0.64% mismatch of one std dev. The structure named VB gets 0.69% mismatch of one dev. It is far from to meet the requirements of a 10bit pipelined ADC. I study one report of a foundry, it mismatch is much larger than 0.1%, too.  

Is it possible to design a 10 bit pipelined ADC using the intra-metal cap? Or the paper and the report gives too pessimistic data?


Best regards,
Yawei
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Paul
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Re: Matching property of intra-metal cap
Reply #1 - May 1st, 2006, 12:53pm
 
Hi Yawei,

I would imagine this type of capacitors is not accurately modeled by foundries because it would require very accurate etching control all over the chip, compared to very local control of MIM capacitors. I'm not too sure about the reasons explaining the large mismatch, but it may be due to the dependency on etching and lithography.

As I'm not a process guy, this is just my very personal guess...

Paul
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ACWWong
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Re: Matching property of intra-metal cap
Reply #2 - May 2nd, 2006, 7:54am
 
You can improve the matching by means of user defined metal fill patterns, to ensure inter metal thickness uniformity it good.

In Al, you will need to read you process guide as to how metal fill is added to planarise the dielectric,
and then design your own fill patterns to get best planarisation around your intra-metal caps... and ensure each cap has the same metal environment, (all levels below, and above)

In Cu, you will need to read your process guide as to the back-laping and "cheesing" process, again to ensure you (not some automatic tool) control the planarisation, and ensure your matched capacitors are given the best chance to have the same cheesing holes/planarisation/dielectric thickness.

As to a number for matching... i'm not sure, but process data with regards to oxide uniformity is usually available. Tolerance wise, oxide thickness & metal thickness can be ~20%, but matching i think i'd have to do a test chip (if of course you have the luxury to do this.)
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ywguo
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Re: Matching property of intra-metal cap
Reply #3 - May 4th, 2006, 4:52am
 
Hi, Wong,

Would you like to explain the back-lapping and cheesing process? Or is there any literature that describes those process?


Thanks
Yawei
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ACWWong
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Re: Matching property of intra-metal cap
Reply #4 - May 4th, 2006, 8:08am
 
hi yawei,

当然,

http://www.semipark.co.kr/upload1/CopperForAdvancedInterconnectIwomsViet.pdf

in the last section talks about the "dishing" problem of copper is usually addressed by "cheesing" holes. Most foundries will have rules as to how big a Cu plate can be before a "cheese hole" is added. I learned of this from the foundry I was using.

I think it may also be covered in
"The Art of Analog Layout" by Alan Hastings
or
http://www.amazon.com/gp/product/0471466107/104-6362119-2928716?v=glance&n=28315...

cheers
aw
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Re: Matching property of intra-metal cap
Reply #5 - Aug 21st, 2006, 2:34pm
 
The "cheese hole" (as in Swiss cheese holes) is all about providing a mechanical support (from an oxide post so to speak) in the middle of sheet copper.

http://www.clarkson.edu/camp/reports/Li.pdf#search=%22cmp%20cu%20dishing%22

The above (see slide 10) has some good illustrations.

For better matching - suggest finding out what is the largest size Cu capacitor you can do without holes in it. Take that and lay it out with perimeters of oxide around them, and interconnect as an array.

A 10 bit pipeline based totally on capacitor matching? That will probably require correction to the pipe, I doubt if it will fly with good INL/DNL without it.
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hyy95
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Re: Matching property of intra-metal cap
Reply #6 - Aug 24th, 2007, 11:58pm
 
I met the same problem. I am designing a 50MHz 10b ADC in a standard CMOS process,  the fab's matching report shows 2% matching for a 20 finger cap unit. Look like in order to get 0.1% matching, i'll need at least 20 such units for a cap. But the problem is, that will result a very large cap that is unacceptable.

My question is, can I connect some of the cap units in series, some in parallel, so that my total cap value won't be too large?
for example, if I put 4 units in series, then connect 4 such cap strings in parallel, I still get a total capatance if 1C from the 16 cap units.
But How do I calculate the variance of such combination? Is there some equation i can follow?

Thanks!
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neoflash
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Re: Matching property of intra-metal cap
Reply #7 - Jan 13th, 2008, 3:19am
 
hyy95 wrote on Aug 24th, 2007, 11:58pm:
I met the same problem. I am designing a 50MHz 10b ADC in a standard CMOS process,  the fab's matching report shows 2% matching for a 20 finger cap unit. Look like in order to get 0.1% matching, i'll need at least 20 such units for a cap. But the problem is, that will result a very large cap that is unacceptable.

My question is, can I connect some of the cap units in series, some in parallel, so that my total cap value won't be too large?
for example, if I put 4 units in series, then connect 4 such cap strings in parallel, I still get a total capatance if 1C from the 16 cap units.
But How do I calculate the variance of such combination? Is there some equation i can follow?

Thanks!


You can write out the equation of your capacitor, and take derivitive on each composing unit. Thus you get the transfer function of each one's random variation.
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