Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Apr 25
th
, 2024, 3:12pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Modeling
›
Passive Devices
› typical inductance variation of on-chip inductor
‹
Previous topic
|
Next topic
›
Pages: 1
typical inductance variation of on-chip inductor (Read 4248 times)
aaron_do
Senior Fellow
Offline
Posts: 1398
typical inductance variation of on-chip inductor
Jan 02
nd
, 2007, 10:54pm
Hi all,
can anyone tell me the typical inductance and Q variation of an on-chip inductor. For example a 5 turn top metal spiral inductor with a 100um core, 10 um width and 2um thickness...any good references?
thanks,
Aaron
Back to top
there is no energy in matter other than that received from the environment - Nikola Tesla
IP Logged
ACWWong
Community Fellow
Offline
Posts: 539
Oxford, UK
Re: typical inductance variation of on-chip induct
Reply #1 -
Jan 3
rd
, 2007, 3:00am
Generally inductance varies very little as it is lateral geometry (total enclosed area & turns) based. I've used kits were worst case L variation was something like 1~2%.
What does vary is Q and SRF. Q can change by about 20%~30% but depends on your frequency of operation (skin loss versus metal R loss, parasitic C value & quality due to ~20% delta on oxide thicknesses and shield/sub impedance variation). I normally design with worst case Q in mind.
As for references.... your pdk/foundry should be the starting point..
cheers
aw
Back to top
IP Logged
aaron_do
Senior Fellow
Offline
Posts: 1398
Re: typical inductance variation of on-chip induct
Reply #2 -
Jan 3
rd
, 2007, 5:05pm
thanks aw
Aaron
Back to top
there is no energy in matter other than that received from the environment - Nikola Tesla
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
»» Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.