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ZaraCattle New Member Offline Posts: 7	How to compile a file Simulation.v ? Apr 16^th, 2007, 4:11am I created a simulated file that i typed code verilog into it(named Simulation.v)I use "$monitor" or "$Display" to print out monitor. But I don't know how to compile them to test my circuit...So how to compile them ?..Everybodd can help me ? Thanks very much...
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Andrew Beckett

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Re: How to compile a file Simulation.v ?
Reply #1 - Apr 16^th, 2007, 5:34am

Well, that rather depends on which tools you're using!

If you're using Cadence's Verilog simulator, you'd type ncverilog Simulation.v if you want to keep the command line interface as simple as possible.

Or you could always read the documentation for the tools you're using. That's probably more efficient than asking a vague question to a large forum and expecting them to guess what tools you're using and what you're trying to do.

Andrew.

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ZaraCattle New Member Offline Posts: 7	Re: How to compile a file Simulation.v ? Reply #2 - Apr 16^th, 2007, 10:29am Ah,sorry to everybody..I'm using Quartus II, a software of altera...And I don't know how to compile file Simulation.v..So Can you show to me some tools that I can simulate my file....Thanks very much....
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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: How to compile a file Simulation.v ? Reply #3 - Apr 17^th, 2007, 6:56am Have you tried the user's guide for Quartus II? Personally, I've never used it, and I don't even know if it's a Verilog simulator! Can you run it from the command line? Are you trying to add the Simulation.v file to a circuit that you're already able to simulate? Or run the .v file as its own simulation?
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ZaraCattle

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Re: How to compile a file Simulation.v ?
Reply #4 - Apr 18^th, 2007, 6:43am

I created a file Simulation.v like this:
Code:

module stimulus;

// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4
fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);


// Set up the monitoring for the signal values
initial
begin
  $monitor($time," A= %b, B=%b, C_IN= %b, --- C_OUT= %b, SUM= %b\n",
				  A, B, C_IN, C_OUT, SUM);
end

// Stimulate inputs
initial
begin
  A = 4'd0; B = 4'd0; C_IN = 1'b0;

  #5 A = 4'd3; B = 4'd4;

  #5 A = 4'd2; B = 4'd5;

  #5 A = 4'd9; B = 4'd9;

  #5 A = 4'd10; B = 4'd15;

  #5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
end
endmodule

I followed on the instructions of my book ....
And I don't know how to run this file that use "$monitor" function.....My book wrote that
Code:

The output of the simulation is shown below.

0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000

5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111

10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111

15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010

20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001

25 A= 1010, B=0101, C_IN= 1,, C_OUT= 1, SUM= 0000

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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: How to compile a file Simulation.v ? Reply #5 - Apr 18^th, 2007, 8:58am Did you read the manual for Quartus II? http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf
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ZaraCattle New Member Offline Posts: 7	Re: How to compile a file Simulation.v ? Reply #6 - Apr 19^th, 2007, 12:30pm Ok..I knew that..But it only describes a result of wave file..I need the result that is console like my book.. ....
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Geoffrey_Coram

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Posts: 1998
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Re: How to compile a file Simulation.v ?
Reply #7 - Apr 20^th, 2007, 5:58am

I ask again: Can you run Quartus II from the command line? Or is it a graphical interface only? Are you sure it's what you want? since the web site (as I was poking around) seemed to indicate it was for simulating FPGAs, and specifically Altera's products.

I have a vague recollection that Dolphin has a free demo version of SMASH (Google "dolphin smash demo"); maybe that will work better for you.

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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jbdavid Community Fellow Offline Posts: 378 Silicon Valley	Re: How to compile a file Simulation.v ? Reply #8 - Dec 18^th, 2008, 7:23pm or you could try Icarus.. its an open source verilog simulator.. or Cver
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