Hi there, I am looking to model a 1bit Sigma Delta DAC
using Verilog AMS or similar. Can anyone tell me if
there is a model already available for use with Cadence?

-Nibblo-

Hi Nibblo,
A DAC model in Vams should not be too difficult, however there is nothing directly available from Cadence. However, the 'bmslib' from Cadence has a model for a behavioral 8-bit DAC, and also a current-steering DAC. These may not directly apply to the Sig-Delta, but it will give you a good idea of where to start.