Hi,
   I am designing a 10b S/H ckt right now. from the papers i read, most 10b adc chips can only get less than 60dB measured SNDR. My question is, how much SNDR, SFDR, THD... do i need from the simulation of a 10b S/H in order to get a not too bad measured result from a finished chip. Or a more general question, how much do you overdesign a circuit?

Thanks
Jerry