Because the non-overlapping time reduces the settling time I would
recommend to design for a short non-overlap time. However, you
need to make sure that the phases never overlap to avoid charge-sharing
(also in presence of process/temperature variations, jitter etc.)
However, if you clock frequency is low the non-overlap time is not that critical since
it has only a small contribution to the overall settling time (and I would add more
margin).

Regards

A lot of thanks to Berti.