Hi,
I am looking for a constant reference loading MDAC structure because of problems with the conventional 1.5-bit MDAC (Please see attached PS).
I am assuming a fully differential arrangement.
If you look carefully, the amplification phase involves connecting the bottom-plate of CS to either +/- VREF or AGND (Common mode reference).
This implies that the load seen by the reference is code-dependent. This can be fixed with dummy cap banks. The more serious problem is that this is a 3-point DAC,
which is not guaranteed to be inherently linear. Any offset on the differential reference levels +/- VREF will show up as DNL.
I considered use of a scheme similar to the one given in the TCAS-II (May 2004 paper) by Yoo, Park, Moon where CS would be split into 2 halves
CS1 and CS2. Now, for +/-VREF, one could connect both halves to either reference, while for providing 0V DAC voltage, you would now
connect CS1 to +VREF and CS2 to -VREF. Thus, only a 2-point DAC is used which is fundamentally linear.
http://web.engr.oregonstate.edu/~moon/research/files/cas2_may_04.pdfHowever, this scheme is not symmetric and will result in increased distortion for very small inputs close to zero. This is often a requirement.
Can anyone suggest a scheme which would avoid the problem of having to use a 3-point DAC but which would give good linearity at low signal levels?
Thanks
Vivek