Two kind of thins must be thought of :
1) matching hardware to model
2) matching hardware to hardware

The first one depends on the process and design kit you're using. For a single fingered transistor you're idea would be correct. Check with your Design Kit manual to find out (if possible) how your transistor was characterized.

The second one might be of more importance when designing a ring oscillator.
Each stage should match perfectly to each other, while occupying as small area as possible (otherwise you'd typically prefer an LC-Osc).
I'd therefore recommend to not use single transistors as dummys, but to share source/drain between dummy transistor and active transistor.
That would mean that you just add another "channel/gate/source" combination to either side of your active transistor.

Thank you very much Stefan and Berti  ;)

What I am still wondering is that:

1) In case that I connect the dummy transistors to each side of a functional transistor (sharing the source/drain region), what about the gate ? Is it necessary to connect the gate of the dummy to the gate of the functional transistor ? Or can I just ground the gate (for NMOS) to deactivate the dummy ?

2) Since my design is working at very high frequency, so if possible, I do not want to attach the dummy transistors to the functional transistor (trying to avoid further loading the functional transistor with more parasitic capacitance). Due to this concern, can I still place the dummy transistors separately from the function transistor and ground all terminals as shown in the figure ? To avoid the edge effect, I agree that sharing the drain/source region would be better, but concerning the contribution of capacitance from the dummy devices, would it also be possible to use separate dummy devices to avoid this contribution ?

Thank you very much to you all again  :)

DYLinux

I may be missing something, but I think you would be better off sharing drains of the dummies with the "functional" transitor.  This is easy to do since they are connected to ground.  In other words, use a single diffusion with four gate stripes and five sets of contacts.

I'm not sure what this will buy you, however, since you only have one "functinoal" transistor.  Ideally, all the matched transistors should be within the same group of dummies.

Although (if supported by your design kit) the easiest way would be to use standard-cell single transistors which are readily characterized using guard ring and everything... you wouldn't need to care about placing dummies then, although you might have to use some more space ...

carlgrace wrote on Oct 2^nd, 2007, 10:15am:



Carl - I've never worked with STI (shallow trench isolation)... how did you arrive at 3um?  And, for the scenario you mention, would the STI "ring" around the transistors be the OD that you refer to?

Rob G,

I came to the 3um number by simulating Vt and Iref shift in devices with varying amounts of dummies until the vt converged.  If you can handle more mismatch, you can handle smaller distance to the OD edge.

yes, OD is the edge of the oxide definition... this is where the STI is applied.

Carl

Hi Stefan, when talking of oscillation frequency you assume an oscillator design?
... and what's about post-layout simulation taking into account the vth-shift?

and Carl, using single devices and making sure that the distance from poly
to the OD-edge is the same for every device, also the influence of stress should
be the same for each device. And devices would still match.?...

Thank you for explanations.

Regards