The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Sep 29th, 2024, 4:20pm
Pages: 1
Send Topic Print
how to reduce the current sinker's noise (Read 2760 times)
Robert
Junior Member
**
Offline



Posts: 18
Xiamen city,Fujian PRO. china
how to reduce the current sinker's noise
Oct 10th, 2007, 6:55am
 
hi,all
  i am designing a 2.5Gbps Transimpedance Amplifier currently, i utilize the cascode topology, the input impedance is greatly reduce to 1/gm, so the input pole is moved far away, however, i found the current sinker contributes large noise current to the input node directly, i have try to increase the Vgs(of course, i still make sure that it is in saturation) and minimize the W/L for a required current, but it still produces near 50% of total input rms referenced noise current. what methodes or techniques you guys would take to reduce its noise based on your experiencement, please let me know, i would really appreciate it, thanks a lot!

best Regards
Nio Lin
Back to top
 
 

i am a gay,who loves ppmm!
View Profile   IP Logged
loose-electron
Senior Fellow
******
Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California
Re: how to reduce the current sinker's noise
Reply #1 - Oct 13th, 2007, 1:21pm
 
As a general rule, any and all current sources are big noise sources.

Consider a differenet topology, suggest getting rid of the current sources in favor of resistors (if applicable, dont know your circuits)

post the schematic for people to make better informed suggestions

jerry
Back to top
 
 

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
View Profile WWW   IP Logged
Robert
Junior Member
**
Offline



Posts: 18
Xiamen city,Fujian PRO. china
Re: how to reduce the current sinker's noise
Reply #2 - Oct 14th, 2007, 7:22pm
 
Dear Jerry,
   thanks for your reply!
   the prototype i used is illustrated as attachment, currently i used the 0.35u CMOS process to design 2.5G/ 4G TIA, except the shunt-shunt feedback structure with cascode (regulated) as input stage, i do not have other solution.

Nio Lin
Back to top
 

1_003.jpg

i am a gay,who loves ppmm!
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.