I don't know if there's any significant difference between a device in a (pwell in a) deep nwell versus one just in the p substrate.

However, I do know that there's a lot of work on the "well proximity effect", where the transistor is significantly altered if the *edge* of an nwell is close to it.  This is because the high-energy implant scatters off the blocking material (photoresist) and into the active area of the device.  You should be able to find more info by searching for WPE.

(Presumably, the high-energy implant passes through the active region of the device that's not near the edge, so the device won't be altered much.)

Hi Berti,

If the foundry offers devices in deep nwell, then it should normally also offer you models based on characterisation
of such devices. Depending on the foundry, there may be some/a lot of differences between these devices (isolated)
and standard nonisolated devices in a pwell process. Typically, I would expect that atleast the basic operation is
quite similar.

Which process is it by the way? Perhaps if someone else is using this process, they could tell you whether the models
are obtained from a characterisation of nwell devices or not.

Regards
Vivek

Berti wrote on Feb 7^th, 2008, 12:10am:

Hi Berti,

I´m currently using a process with special deep nwell models. However - as Vivek pointed out correctly - basic operation is quite similar for the isolated and non-isolated devices. The differences mainly reside on the isolation junctions modeling, these junctions obviously not being present in the case of non-isolated devices. These might play a role when operating the device at high temperature (leakage currents) or might become important in case the device is, for example, connected to input/output interfaces that can be subjected to larger than normal operation voltages.
Finally, parasitics are certainly different and might also play a role in the device AC response, although this might only be important at relatively high frequencies.

Regards
Tosei

Hi all,

I am wondering if nMOS in floating DNW is not good for latch-up immunity.
Can anyone share the knowledge?

Thanks very much!

I helped define the deep n-well structures in the IBM SiGe processes.

They don't help that much with noise coupling.

Whats the issue?

Latch up and isolation? Its all about keeping things properly reverse biased and liberal use of contacts in the biasing.