Monkeybad
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Posts: 31
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Thanks! Berti! Your answer is very helpful. As I know, the jitter comes from two sources. One comes from the reference clock, PFD, charge pump, and it passes the loop-filter so it is a low-pass signal. Another one comes from the VCO directly, and it can't be filtered by loop filter so it is a high-pass signal. So what you mean is that: (1)For ring oscillator, the jitter in VCO is dominated so I set the Kvco higher to suppress the jitter. (2)For LC tank PLL, like GSM transceivers, the jitter is low in VCO because we use the LC tank structure. The jitter from reference clock is dominated so I set the Kvco lower for not to disturbance the LC tank VCO. But the tuning range is smaller. Is it correct?
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