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IDDQ (Read 4001 times)
HdrChopper
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IDDQ
Feb 28th, 2008, 4:44pm
 
Hi,

I have for the first time to implement IDDQ testing on a chip, but actually the digital circuits are just a few (mainly an oscillator and some combinational logic). Does anybody has suggestions or outlines about what should I use to minimize the overhead of the IDDQ test circuit?

Many thanks
Tosei
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Geoffrey_Coram
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Re: IDDQ
Reply #1 - Mar 19th, 2008, 8:12am
 
I wonder if the fact that you didn't define IDDQ is related to the fact that no one has answered your post...
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HdrChopper
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Re: IDDQ
Reply #2 - Mar 20th, 2008, 6:58am
 
Hi Geoffrey,

May be you´re right. Here goes a common definition:

"IDDQ refers to the quiescent current drawn by CMOS circuit from the supply when all inputs are held at static values. Low IDDQ (or leakage current) drawn by fault-free CMOS circuits is compared against predetermined threshold".

Thanks
Tosei
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