Hi!
I simulate internal power ("rise_power", "fall_power", internal power group in .lib format synopsys) for digital library cells. But i do it manually, w/o special tools like nanochar . In particular, i use internal function of spice simulator. In simplest cells (invs, buffs) the following assumption works:
Internal power = total  power –C_load*VDD*VDD/2, where  
total  power = integral i_vdd(t) during rise/fall time for output signal* VDD
In some cases, fall_power is negative.  
Results looks good  as in an available sample file. But in complex cells (flip-flops for example), in sample .lib file internal power poorly depends from C_load, does not depend almost. I have different results, for big load capacitances (I use same templates)  internal power exceeds ten times power, which presented in  sample file.
?????
Thanks for help!