The answer to this is going to be unique to your transistors and foundry selection. Suggest that you do a mismatch study from the statistical data on the foundry models, and look at that in conjunction wity your dynamic switching mismatch characteristics, and your dependence on output voltage variance effects on currents. They will all play in to the answer.
email_gz wrote on Oct 5th, 2008, 11:57pm:Hello All:
Does anyone know the value of how much mismatch percentage of the Charge Pump: |Iup-Idn|/Inormal in now days CMOS?
The value is better from the published paper, so I can use this
paper as an index.
Thank you very much!